Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
487 of 792
NXP Semiconductors
UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
(9)
(10)
8.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL -
0xE004 8018)
This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read
at any time but can only be written if the RM bit in CANmod is 1. The default value (after
hardware reset) is 96.
at any time but can only be written if the RM bit in CANmod is 1. The default value (after
hardware reset) is 96.
Note that a content change of the Error Warning Limit Register is possible only if the
Reset Mode was entered previously. An Error Status change (Status Register) and an
Error Warning Interrupt forced by the new register content will not occur until the Reset
Mode is cancelled again.
Reset Mode was entered previously. An Error Status change (Status Register) and an
Error Warning Interrupt forced by the new register content will not occur until the Reset
Mode is cancelled again.
8.8 Status Register (CAN1SR - 0xE004 401C, CAN2SR - 0xE004 801C)
This register contains three status bytes in which the bits not related to transmission are
identical to the corresponding bits in the Global Status Register, while those relating to
transmission reflect the status of each of the 3 Tx Buffers.
identical to the corresponding bits in the Global Status Register, while those relating to
transmission reflect the status of each of the 3 Tx Buffers.
t
TSEG1
t
SCL
TSEG1
1
+
(
)
×
=
t
TSEG2
t
SCL
TSEG2
1
+
(
)
×
=
Table 426. Error Warning Limit register (CAN1EWL - address 0xE004 4018, CAN2EWL -
address 0xE004 8018) bit description
Bit Symbol Function
Reset
Value
Value
RM
Set
Set
7:0 EWL
During CAN operation, this value is compared to both the Tx and
Rx Error Counters. If either of these counter matches this value,
the Error Status (ES) bit in CANSR is set.
Rx Error Counters. If either of these counter matches this value,
the Error Status (ES) bit in CANSR is set.
96
10
= 0x60 X
Table 427. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description
Bit
Symbol Value
Function
Reset
Value
Value
RM
Set
Set
0
RBS
Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
0
0
1
DOS
Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
0
0
2
TBS1
Transmit Buffer Status 1.
1
1
0(locked)
Software cannot access the Tx Buffer 1 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
1(released)
Software may write a message into the Transmit Buffer 1 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
CANxTID, CANxTDA, and CANxTDB registers.
3
TCS1
Transmission Complete Status.
1
x
0(incomplete)
The previously requested transmission for Tx Buffer 1 is not complete.
1(complete)
The previously requested transmission for Tx Buffer 1 has been successfully
completed.
completed.
4
RS
Receive Status. This bit is identical to the RS bit in the GSR.
1
0