Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
513 of 792
NXP Semiconductors
UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
17.2.3 Setting the interrupt pending bits (IntPnd 63 to 0)
The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN
message and if the interrupt of the according FullCAN Object is enabled (enable bit
FCANIntxEn) is set).
message and if the interrupt of the according FullCAN Object is enabled (enable bit
FCANIntxEn) is set).
During the last write access from the data storage of a FullCAN message object the
interrupt pending bit of a FullCAN object (IntPndx) gets asserted.
interrupt pending bit of a FullCAN object (IntPndx) gets asserted.
17.2.4 Clearing the interrupt pending bits (IntPnd 63 to 0)
Each of the FullCAN Interrupt Pending requests gets cleared when the semaphore bits of
a message object are cleared by Software (ARM CPU).
a message object are cleared by Software (ARM CPU).
17.2.5 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0)
The Message Lost bit of a FullCAN message object gets asserted in case of an accepted
FullCAN message and when the FullCAN Interrupt of the same object is asserted already.
FullCAN message and when the FullCAN Interrupt of the same object is asserted already.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit
is set already.
Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit
is set already.
17.2.6 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to
0)
The Message Lost bit of a FullCAN message object gets cleared when the FullCAN
Interrupt of the same object is not asserted.
Interrupt of the same object is not asserted.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit
is not set.
Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit
is not set.
17.3 Set and clear mechanism of the FullCAN interrupt
Special precaution is needed for the built-in set and clear mechanism of the FullCAN
Interrupts. The following text illustrates how the already existing Semaphore Bits (see
Interrupts. The following text illustrates how the already existing Semaphore Bits (see
for more details) and how the new introduced
features (IntPndx, MsgLstx) will behave.
17.3.1 Scenario 1: Normal case, no message lost
message is stored in the FullCAN Message Object Section. After storage the message is
read out by Software (ARM CPU).
read out by Software (ARM CPU).