Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal 
goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is 
set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on 
the last clock edge where data is sampled.

There are four registers that control the SPI peripheral. They are described in detail in 

The SPI control register contains a number of programmable bits used to control the 
function of the SPI block. The settings for this register must be set up prior to a given data 
transfer taking place.

The SPI status register contains read only bits that are used to monitor the status of the 
SPI interface, including normal functions, and exception conditions. The primary purpose 
of this register is to detect completion of a data transfer. This is indicated by the SPIF bit. 
The remaining bits in the register are exception condition indicators. These exceptions will 
be described later in this section.

The SPI data register is used to provide the transmit and receive data bytes. An internal 
shift register in the SPI block logic is used for the actual transmission and reception of the 
serial data. Data is written to the SPI data register for the transmit case. There is no buffer 
between the data register and the internal shift register. A write to the data register goes 
directly into the internal shift register. Therefore, data should only be written to this register 
when a transmit is not currently in progress. Read data is buffered. When a transfer is 
complete, the receive data is transferred to a single byte data buffer, where it is later read. 
A read of the SPI data register returns the value of the read data buffer.

The SPI clock counter register controls the clock rate when the SPI block is in master 
mode. This needs to be set prior to a transfer taking place, when the SPI block is a 
master. This register has no function when the SPI block is a slave.

The I/Os for this implementation of SPI are standard CMOS I/Os. The open drain SPI 
option is not implemented in this design. When a device is set up to be a slave, its I/Os are 
only active when it is selected by the SSEL signal being active.

The following sequence describes how one should process a data transfer with the SPI 
block when it is set up to be the master. This process assumes that any prior data transfer 
has already completed.

1. Set the SPI clock counter register to the desired clock rate.

2. Set the SPI control register to the desired settings.

3. Write the data to transmitted to the SPI data register. This write starts the SPI data 

transfer.

4. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set 

after the last cycle of the SPI data transfer.