Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

The CRC generator calculates the CRC checksum for all bits before the CRC code. This 
includes the start bit, transmitter bit, command index, and command argument (or card 
status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long 
response format. Note that the start bit, transmitter bit and the six reserved bits are not 
used in the CRC calculation.

The CRC checksum is a 7 bit value:

    CRC[6:0] = Remainder [(M(x) 

× x

7

 ) / G(x)]

    G(x) = x

7

 + x

3

 + 1

    M(x) = (start bit) 

× x

39

 + ... + (last bit before CRC) 

× x

0

 , or

    M(x) = (start bit) 

× x

119

 + ... + (last bit before CRC) 

× x

0

The card data bus width can be programmed using the clock control register. If the wide 
bus mode is enabled, data is transferred at four bits per clock cycle over all four data 
signals (MCIDAT[3:0]). If the wide bus mode is not enabled, only one bit per clock cycle is 
transferred over MCIDAT0.

Depending on the transfer direction (send or receive), the Data Path State Machine 
(DPSM) moves to the WAIT_S or WAIT_R state when it is enabled:

Send: The DPSM moves to the WAIT_S state. If there is data in the send FIFO, the 
DPSM moves to the SEND state, and the data path subunit starts sending data to a 
card.

Receive: The DPSM moves to the WAIT_R state and waits for a start bit. When it 
receives a start bit, the DPSM moves to the RECEIVE state, and the data path subunit 
starts receiving data from a card.

The DPSM operates at MCICLK frequency. Data on the card bus signals is synchronous 
to the rising edge of MCICLK. The DPSM has six states, as shown in 

CmdRespEnd

Set if response CRC is OK.

CmdCrcFail

Set if response CRC fails.

CmdSent

Set when command (that does not require response) is sent.

CmdTimeOut

Response timeout.

CmdActive

Command transfer in progress.