Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

The synchronization logic will synchronize the serial clock generator with the clock pulses 
on the SCL line from another device. If two or more master devices generate clock pulses, 
the “mark” duration is determined by the device that generates the shortest “marks,” and 
the “space” duration is determined by the device that generates the longest “spaces”. 

 shows the synchronization procedure.

 

A slave may stretch the space duration to slow down the bus master. The space duration 
may also be stretched for handshaking purposes. This can be done after each bit or after 
a complete byte transfer. the I

2

C block will stretch the SCL space duration after a byte has 

been transmitted or received and the acknowledge bit has been transferred. The serial 
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is 
cleared.

This programmable clock pulse generator provides the SCL clock pulses when the I

2

C 

block is in the master transmitter or master receiver mode. It is switched off when the I

2

C 

block is in a slave mode. The I

2

C output clock frequency and duty cycle is programmable 

via the I

2

C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH 

registers for details. The output clock pulses have a duty cycle as programmed unless the 
bus is synchronizing with other SCL clock sources as described above.

The timing and control logic generates the timing and control signals for serial byte 
handling. This logic block provides the shift pulses for I2DAT, enables the comparator, 
generates and detects start and stop conditions, receives and transmits acknowledge bits, 
controls the master and slave modes, contains interrupt request logic, and monitors the 
I

2

C bus status.

The I

2

C control register contains bits used to control the following I

2

C block functions: start 

and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, 
and acknowledgment.

(1) Another device pulls the SCL line low before this I

2

C has timed a complete high time. The other 

device effectively determines the (shorter) HIGH period.

(2) Another device continues to pull the SCL line low after this I

2

C has timed a complete low time and 

released SCL. The I

2

C clock generator is forced to wait until SCL goes HIGH. The other device 

effectively determines the (longer) LOW period.

(3) The SCL line is released , and the clock generator begins timing the HIGH time.

SDA line

SCL line

(2)

(1)

(3)

high

period

low

period

(1)