Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

The I

2

S interface is configured using the following registers:

1. Power: In the PCONP register (

), set bit PCI2S.

Remark: On reset, the I

2

S interface is disabled (PCI2S = 0).

2. Clock: In PCLK_SEL1 select PCLK_I2S, see 

3. Pins: Select I

2

S pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to 

). 

4. Interrupts are enabled in the VIC using the VICIntEnable register (

The I

2

S bus provides a standard communication interface for digital audio applications.

The I

2

S bus specification defines a 3-wire serial bus, having 1 data, 1 clock, and one word 

select signal. The basic I

2

S connection has one master, which is always the master, and 

one slave. The I

2

S interface on the LPC2400 provides a separate transmit and receive 

channel, each of which can operate as either a master or a slave.

The I2S output can operate in both master and slave mode, independent of the I2S 
input.

Capable of handling 8, 16, and 32 bit word sizes.

Mono and stereo audio data supported.

The sampling frequency can range (in practice) from 16 - 96 kHz. (16, 22.05, 32, 44.1, 
48, 96 kHz) for audio applications.

Word Select period in master mode is configurable (separately for I

2

S input and I2S 

output).

Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

Generates interrupt requests when buffer levels cross a programmable boundary.

Two DMA requests, controlled by programmable buffer levels. These are connected 
to the General Purpose DMA block.

Controls include reset, stop and mute options separately for I

2

S input and I

2

S output.

The I

2

S performs serial data out via the transmit channel and serial data in via the receive 

channel. These support the NXP Inter IC Audio format for 8, 16 and 32 bits audio data 
both for stereo and mono modes. Configuration, data access and control is performed by 
a APB register set. Data streams are buffered by FIFOs with a depth of 8 bytes.

The I

2

S receive and transmit stage can operate independently in either slave or master 

mode. Within the I

2

S module the difference between these modes lies in the word select 

(WS) signal which determines the timing of data transmissions. Data words start on the