Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
616 of 792
NXP Semiconductors
UM10237
Chapter 23: LPC24XX I
2
S interface
5.6 DMA Configuration Register 1 (I2SDMA1 - 0xE008 8014)
The I2SDMA1 register controls the operation of DMA request 1. The function of bits in
I2SDMA1 are shown in
I2SDMA1 are shown in
. Refer to the General Purpose DMA Controller
chapter for details of DMA operation.
5.7 DMA Configuration Register 2 (I2SDMA2 - 0xE008 8018)
The I2SDMA2 register controls the operation of DMA request 2. The function of bits in
I2SDMA2 are shown in
I2SDMA2 are shown in
5.8 Interrupt Request Control Register (I2SIRQ - 0xE008 801C)
The I2SIRQ register controls the operation of the I
2
S interrupt request. The function of bits
in I2SIRQ are shown in
15:8
rx_level
Reflects the current level of the Receive FIFO.
0
23:16 tx_level
Reflects the current level of the Transmit FIFO.
0
31:24 -
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
value read from a reserved bit is not defined.
NA
Table 536: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description
Bit
Symbol
Description
Reset
Value
Value
Table 537: DMA Configuration register 1 (I2SDMA1 - address 0xE008 8014) bit description
Bit
Symbol
Description
Reset
Value
Value
0
rx_dma1_enable
When 1, enables DMA1 for I
2
S receive.
0
1
tx_dma1_enable
When 1, enables DMA1 for I
2
S transmit.
0
7:2
Unused
Unused.
0
15:8
rx_depth_dma1
Set the FIFO level that triggers a receive DMA request on
DMA1.
DMA1.
0
23:16
tx_depth_dma1
Set the FIFO level that triggers a transmit DMA request on
DMA1.
DMA1.
0
31:24
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
NA
Table 538: DMA Configuration register 2 (I2SDMA2 - address 0xE008 8018) bit description
Bit
Symbol
Description
Reset
Value
Value
0
rx_dma2_enable
When 1, enables DMA1 for I
2
S receive.
0
1
tx_dma2_enable
When 1, enables DMA1 for I
2
S transmit.
0
7:2
Unused
Unused.
0
15:8
rx_depth_dma2
Set the FIFO level that triggers a receive DMA request
on DMA2.
on DMA2.
0
23:16
tx_depth_dma2
Set the FIFO level that triggers a transmit DMA request
on DMA2.
on DMA2.
0
31:24
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
reserved bits. The value read from a reserved bit is not
defined.
NA