Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

Free running timer.

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an 
externally-supplied clock, and can optionally generate interrupts or perform other actions 
at specified timer values, based on four match registers. It also includes four capture 
inputs to trap the timer value when an input signal transitions, optionally generating an 
interrupt.

 gives a brief summary of each of the Timer/Counter related pins.

 

Software can select multiple pins for most of the CAP or MAT functions in the Pin Select 
registers, which are described in 

. When more than one pin is selected for a 

MAT output, all such pins are driven identically. When more than one pin is selected for a 
CAP input, the pin with the lowest port number is used.

Each Timer/Counter contains the registers shown in 

 ("Reset Value" refers to 

the data stored in used bits only; it does not include reserved bits content). More detailed 
descriptions follow.

CAP0[1:0]
CAP1[1:0] 
CAP2[1:0]
CAP3[1:0]

Input

Capture Signals- A transition on a capture pin can be configured to load one 
of the Capture Registers with the value in the Timer Counter and optionally 
generate an interrupt. Capture functionality can be selected from a number 
of pins. When more than one pin is selected for a Capture input on a single 
TIMER0/1 channel, the pin with the lowest Port number is used

Timer/Counter block can select a capture signal as a clock source instead of 
the PCLK derived clock. For more details see 

.

MAT0[1:0]
MAT1[2:0]
MAT2[3:0]
MAT3[3:0]

Output

External Match Output 0/1- When a match register 0/1 (MR3:0) equals the 
timer counter (TC) this output can either toggle, go low, go high, or do 
nothing. The External Match Register (EMR) controls the functionality of this 
output. Match Output functionality can be selected on a number of pins in 
parallel.