Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
711 of 792
1.
Basic configuration
The GPDMA is configured using the following registers:
1. Power: In the PCONP register (
), set bit PCGPDMA.
Remark: On reset, the GPDMA is disabled (PCGPDMA = 0).
2. Clock: see
.
3. Interrupts are enabled in the VIC using the VICIntEnable register (
.
2.
Introduction
The General Purpose DMA Controller (GPDMA) is an AMBA AHB compliant peripheral
allowing selected LPC2400 peripherals to have DMA support.
allowing selected LPC2400 peripherals to have DMA support.
3.
Features of the GPDMA
•
Two DMA channels. Each channel can support a unidirectional transfer.
•
The GPDMA provides 16 peripheral DMA request lines. Some of these are connected
to peripheral functions that support DMA: the SD/MMC, two SSP, and I2S interfaces.
to peripheral functions that support DMA: the SD/MMC, two SSP, and I2S interfaces.
•
Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
•
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
peripheral-to-peripheral transfers.
•
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
the source and destination areas do not have to occupy contiguous areas of memory.
•
Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time the channel with the
highest priority is serviced first.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time the channel with the
highest priority is serviced first.
•
AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
DMA control registers over the AHB slave interface.
•
One AHB bus master for transferring data. This interface transfers data when a DMA
request goes active.
request goes active.
•
32-bit AHB master bus width.
•
Incrementing or non-incrementing addressing for source and destination.
•
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.
•
Internal four-word FIFO per channel.
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA)
controller
controller
Rev. 02 — 19 December 2008
User manual