Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
717 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
4.2.10 Channel hardware
Each stream is supported by a dedicated hardware channel, including source and
destination controllers, and a FIFO. This enables better latency than a DMA controller with
only a single hardware channel shared between several DMA streams and simplifies the
control logic.
destination controllers, and a FIFO. This enables better latency than a DMA controller with
only a single hardware channel shared between several DMA streams and simplifies the
control logic.
4.2.11 DMA request priority
DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 1
has the lowest priority.
has the lowest priority.
If the GPDMA is transferring data for the lower priority channel and then the higher priority
channel goes active, it completes the number of transfers delegated to the master
interface by the lower priority channel before switching over to transfer data for the higher
priority channel. In the worst case this is as large as a one quadword. Channel 1 in the
GPDMA is designed so that it cannot saturate the AHB bus. If it goes active, the GPDMA
relinquishes control of the bus (for a bus cycle), after four transfers of the programmed
size (irrespective of the size of transfer). This enables other AHB masters to access the
bus.
channel goes active, it completes the number of transfers delegated to the master
interface by the lower priority channel before switching over to transfer data for the higher
priority channel. In the worst case this is as large as a one quadword. Channel 1 in the
GPDMA is designed so that it cannot saturate the AHB bus. If it goes active, the GPDMA
relinquishes control of the bus (for a bus cycle), after four transfers of the programmed
size (irrespective of the size of transfer). This enables other AHB masters to access the
bus.
It is recommended that memory-to-memory transactions use the low priority channel.
Otherwise other (lower priority) AHB bus masters are prevented from accessing the bus
during GPDMA memory-to-memory transfer.
Otherwise other (lower priority) AHB bus masters are prevented from accessing the bus
during GPDMA memory-to-memory transfer.
4.2.12 Interrupt generation
A combined interrupt output is generated as an OR function of the individual interrupt
requests of the GPDMA, and is connected to the LPC2400 interrupt controller.
requests of the GPDMA, and is connected to the LPC2400 interrupt controller.
4.2.13 The completion of the DMA transfer indication
The completion of the DMA transfer is indicated by:
1. The transfer count reaching 0 if the GPDMA is performing flow control, OR
2. The peripheral setting the DMA Last Word Request Input (DMACLSREQ) or the DMA
Last Burst Request Input (DMALBREQ) if the peripheral is performing flow control.
, SSP0, SSP1 and I2S do not use DMA
Last Word Request Input nor DMA Last Burst Request Input. Therefore there will be no
indication of completion if SSP0, SSP1 and I2S are performing the flow control.
indication of completion if SSP0, SSP1 and I2S are performing the flow control.
4.3 DMA system connections
The connection of the GPDMA to the supported peripheral devices depends on the DMA
functions implemented in those peripherals.
functions implemented in those peripherals.
shows the DMA Request
numbers used by the supported peripherals.
Table 652. DMA Connections
Peripheral Function DMA Single
Request Input
DMA Burst
Request Input
Request Input
DMA Last Word
Request Input
Request Input
DMA Last Burst
Request Input
Request Input
SSP0 Tx
0
0
-
-
SSP0 Rx
1
1
-
-
SSP1 Tx
2
2
-
-