Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

– The DMA stream has the highest pending priority.

– The GPDMA is the bus master of the AHB bus.

4. If an error occurs while transferring the data an error interrupt is generated, then 

finishes.

5. Decrement the transfer count if the GPDMA is performing the flow control.

6. If the transfer has completed (indicated by the transfer count reaching 0 if the GPDMA 

is performing flow control, or by the peripheral sending a DMA request if the 
peripheral is performing flow control):

– The GPDMA responds with a DMA acknowledge to the source peripheral.

– Further source DMA requests are ignored.

7. When the destination DMA request goes active and there is data in the GPDMA FIFO, 

transfer data into the destination peripheral.

8. If an error occurs while transferring the data, an error interrupt is generated and 

disables the DMA stream, and the flow sequence ends.

9. If the transfer has completed it is indicated by the transfer count reaching 0 if the 

GPDMA is performing flow control, or by sending a DMA request if the peripheral is 
performing flow control. The following happens:

– The GPDMA responds with a DMA acknowledge to the destination peripheral.

– The terminal count interrupt is generated (this interrupt can be masked).

– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr, 

DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back 
to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow 
sequence ends.

For a memory-to-memory DMA flow the following sequence occurs:

1. Program and enable the DMA channel.

2. Transfer data whenever the DMA channel has the highest pending priority and the 

GPDMA gains mastership of the AHB bus.

3. If an error occurs while transferring the data generate an error interrupt and disable 

the DMA stream.

4. Decrement the transfer count.

5. If the count has reached zero:

– Generate a terminal count interrupt (the interrupt can be masked).

– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr, 

DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back 
to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow 
sequence ends.

Note: Memory-to-memory transfers should be programmed with a low channel priority, 
otherwise other DMA channels cannot access the bus until the memory-to-memory 
transfer has finished, or other AHB masters cannot perform any transaction.