Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

;is not aware of the VIC interrupt priority hardware so trick

;rm_irqhandler2 to return here

STMFD sp!, {ip,pc}

LDR pc, 

rm_irqhandler2

;rm_irqhandler2 returns here

MSR  cpsr_c, #0x52 

;Disable irq, move to IRQ mode

MSR  spsr, r12 

;Restore SPSR from r12

STMFD sp!, {r0}

LDR r0, 

=VICBaseAddr

STR  r1, [r0,#VICVectAddrOffset] 

;Acknowledge Non Vectored irq has finished

LDMFD sp!, {r12,r14,r0} 

;Restore registers

SUBS  pc, r14, #4 

;Return to the interrupted instruction

END

RealMonitor was built with the following options:

RM_OPT_DATALOGGING=FALSE

This option enables or disables support for any target-to-host packets sent on a non 
RealMonitor (third-party) channel.

RM_OPT_STOPSTART=TRUE

This option enables or disables support for all stop and start debugging features.

RM_OPT_SOFTBREAKPOINT=TRUE

This option enables or disables support for software breakpoints.

RM_OPT_HARDBREAKPOINT=TRUE

Enabled for cores with EmbeddedICE-RT. This device uses ARM-7TDMI-S Rev 4 with 
EmbeddedICE-RT.

RM_OPT_HARDWATCHPOINT=TRUE

Enabled for cores with EmbeddedICE-RT. This device uses ARM-7TDMI-S Rev 4 with 
EmbeddedICE-RT.

RM_OPT_SEMIHOSTING=FALSE

This option enables or disables support for SWI semi-hosting. Semi-hosting provides 
code running on an ARM target use of facilities on a host computer that is running an 
ARM debugger. Examples of such facilities include the keyboard input, screen output, 
and disk I/O.

RM_OPT_SAVE_FIQ_REGISTERS=TRUE

This option determines whether the FIQ-mode registers are saved into the registers 
block when RealMonitor stops.