Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
773 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
4.
Figures
Fig 10. Reset block diagram including the wakeup timer.33
Fig 11. Example of start-up after reset. . . . . . . . . . . . . . .34
Fig 12. Clock generation for the LPC2400. . . . . . . . . . . .42
Fig 13. Oscillator modes and models: a) slave mode of
Fig 11. Example of start-up after reset. . . . . . . . . . . . . . .34
Fig 12. Clock generation for the LPC2400. . . . . . . . . . . .42
Fig 13. Oscillator modes and models: a) slave mode of
X1
/
X2
evaluation44
Fig 15. EMC block diagram . . . . . . . . . . . . . . . . . . . . . . .69
Fig 16. 32 bit bank external memory interfaces ( bits
Fig 16. 32 bit bank external memory interfaces ( bits
Fig 19. Typical memory configuration diagram . . . . . . . .99
Fig 20. Simplified block diagram of the Memory Accelerator
Fig 20. Simplified block diagram of the Memory Accelerator
Fig 23. LPC2458 pinning TFBGA180 package . . . . . . . 119
Fig 24. LPC2400 pinning LQFP208 package . . . . . . . .120
Fig 25. LPC2400 pinning TFBGA208 package . . . . . . .120
Fig 26. Ethernet block diagram . . . . . . . . . . . . . . . . . . .212
Fig 27. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .216
Fig 28. Receive descriptor memory layout. . . . . . . . . . .241
Fig 29. Transmit descriptor memory layout . . . . . . . . . .244
Fig 30. Transmit example memory and registers. . . . . .255
Fig 31. Receive Example Memory and Registers . . . . .261
Fig 32. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .266
Fig 33. Receive filter block diagram. . . . . . . . . . . . . . . .268
Fig 34. Receive Active/Inactive state machine . . . . . . .272
Fig 35. Transmit Active/Inactive state machine . . . . . . .273
Fig 36. LCD controller block diagram. . . . . . . . . . . . . . .286
Fig 37. Cursor movement . . . . . . . . . . . . . . . . . . . . . . .294
Fig 38. Cursor clipping . . . . . . . . . . . . . . . . . . . . . . . . . .295
Fig 39. Cursor image format . . . . . . . . . . . . . . . . . . . . .296
Fig 40. Power up and power down sequences . . . . . . .302
Fig 41. Horizontal timing for STN displays. . . . . . . . . . .322
Fig 42. Vertical timing for STN displays . . . . . . . . . . . . .323
Fig 43. Horizontol timing for TFT displays . . . . . . . . . . .323
Fig 44. Vertical timing for TFT displays . . . . . . . . . . . . .324
Fig 45. USB device controller block diagram . . . . . . . . .331
Fig 46. USB MaxPacketSize register array indexing . . .349
Fig 24. LPC2400 pinning LQFP208 package . . . . . . . .120
Fig 25. LPC2400 pinning TFBGA208 package . . . . . . .120
Fig 26. Ethernet block diagram . . . . . . . . . . . . . . . . . . .212
Fig 27. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .216
Fig 28. Receive descriptor memory layout. . . . . . . . . . .241
Fig 29. Transmit descriptor memory layout . . . . . . . . . .244
Fig 30. Transmit example memory and registers. . . . . .255
Fig 31. Receive Example Memory and Registers . . . . .261
Fig 32. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .266
Fig 33. Receive filter block diagram. . . . . . . . . . . . . . . .268
Fig 34. Receive Active/Inactive state machine . . . . . . .272
Fig 35. Transmit Active/Inactive state machine . . . . . . .273
Fig 36. LCD controller block diagram. . . . . . . . . . . . . . .286
Fig 37. Cursor movement . . . . . . . . . . . . . . . . . . . . . . .294
Fig 38. Cursor clipping . . . . . . . . . . . . . . . . . . . . . . . . . .295
Fig 39. Cursor image format . . . . . . . . . . . . . . . . . . . . .296
Fig 40. Power up and power down sequences . . . . . . .302
Fig 41. Horizontal timing for STN displays. . . . . . . . . . .322
Fig 42. Vertical timing for STN displays . . . . . . . . . . . . .323
Fig 43. Horizontol timing for TFT displays . . . . . . . . . . .323
Fig 44. Vertical timing for TFT displays . . . . . . . . . . . . .324
Fig 45. USB device controller block diagram . . . . . . . . .331
Fig 46. USB MaxPacketSize register array indexing . . .349
Fig 47. Interrupt event handling . . . . . . . . . . . . . . . . . . 361
Fig 48. UDCA Head register and DMA Descriptors . . . 374
Fig 49. Isochronous OUT endpoint operation example. 382
Fig 50. Data transfer in ATLE mode . . . . . . . . . . . . . . . 383
Fig 51. USB Host controller block diagram . . . . . . . . . . 389
Fig 52. USB OTG controller block diagram. . . . . . . . . . 394
Fig 53. USB OTG port configuration: port U1 OTG
Fig 48. UDCA Head register and DMA Descriptors . . . 374
Fig 49. Isochronous OUT endpoint operation example. 382
Fig 50. Data transfer in ATLE mode . . . . . . . . . . . . . . . 383
Fig 51. USB Host controller block diagram . . . . . . . . . . 389
Fig 52. USB OTG controller block diagram. . . . . . . . . . 394
Fig 53. USB OTG port configuration: port U1 OTG
Fig 54. USB OTG port configuration: VP_VM mode . . . 397
Fig 55. USB OTG port configuration: port U2 host, port U1
Fig 55. USB OTG port configuration: port U2 host, port U1
Fig 58. USB OTG interrupt handling . . . . . . . . . . . . . . . 409
Fig 59. USB OTG controller with software stack . . . . . . 411
Fig 60. Hardware support for B-device switching from
Fig 59. USB OTG controller with software stack . . . . . . 411
Fig 60. Hardware support for B-device switching from
Fig 64. Clocking and power control. . . . . . . . . . . . . . . . 419
Fig 65. Autobaud a) mode 0 and b) mode 1 waveform 436
Fig 66. Algorithm for setting UART dividers . . . . . . . . . 439
Fig 67. UART0, 2 and 3 block diagram . . . . . . . . . . . . . 442
Fig 68. Auto-RTS Functional Timing . . . . . . . . . . . . . . . 454
Fig 69. Auto-CTS Functional Timing . . . . . . . . . . . . . . . 455
Fig 70. Auto-baud a) mode 0 and b) mode 1 waveform 461
Fig 71. Algorithm for setting UART dividers . . . . . . . . . 463
Fig 72. UART1 block diagram . . . . . . . . . . . . . . . . . . . . 466
Fig 73. CAN controller block diagram . . . . . . . . . . . . . . 469
Fig 74. Transmit buffer layout for standard and extended
Fig 65. Autobaud a) mode 0 and b) mode 1 waveform 436
Fig 66. Algorithm for setting UART dividers . . . . . . . . . 439
Fig 67. UART0, 2 and 3 block diagram . . . . . . . . . . . . . 442
Fig 68. Auto-RTS Functional Timing . . . . . . . . . . . . . . . 454
Fig 69. Auto-CTS Functional Timing . . . . . . . . . . . . . . . 455
Fig 70. Auto-baud a) mode 0 and b) mode 1 waveform 461
Fig 71. Algorithm for setting UART dividers . . . . . . . . . 463
Fig 72. UART1 block diagram . . . . . . . . . . . . . . . . . . . . 466
Fig 73. CAN controller block diagram . . . . . . . . . . . . . . 469
Fig 74. Transmit buffer layout for standard and extended
Fig 77. Local self test (high-speed CAN Bus example). 472
Fig 78. Entry in FullCAN and individual standard identifier
Fig 78. Entry in FullCAN and individual standard identifier