Renesas 4513 ユーザーズマニュアル

4513/4514 Group User’s Manual

1-31

T4F

T3F

10

01

00

W3

1

,W3

0

0

1

W3

3

(Note 3)

0

1

W4

3

(Note 3)

11

T1F

(T2AB)

T2F

(TAB2)

0

1

W2

3

(Note 3)

0

1

(Note 3)

W1

1

(TR1AB)

T1AB

T1AB

(TAB1)

(T4AB)

(TAB4)

(TR3AB)

T3AB

T3AB

(TAB3)

Q

R

S

1 - - - - - - - - - - - 15 16

WDF1 WDF2

WEF

10

01

00

W2

1

,W2

0

11

10

01

00

W4

1

,W4

0

11

Timer 4 
interrupt

Timer 3 

interrupt

Not available

WRST instruction

Timer 2 underflow signal

Timer 1 (8)

Timer 1 
interrupt

Reload register R1 (8)

Register B Register A

Timer 1 underflow signal

Timer 2 (8)

Reload register R2 (8)

Register B Register A

Timer 3 (8)

Reload register R3 (8)

Register B Register A

Timer 3 underflow signal

Timer 4 (8)

Reload register R4 (8)

Register B Register A

Instruction clock

16-bit timer (WDT)

System reset

Reset signal

Timer 2 
interrupt

Data is set automatically from each reload 
register when timer 1, 2, 3, or 4 underflows 
(auto-reload function)

Notes 1: Timer 1 count start synchronous circuit is set 

by the valid edge of P3

0

/INT0 pin selected by 

bits 1 (I1

1

) and 2 (I1

2

) of register I1.

2: Timer 3 count start synchronous circuit is set 

by the valid edge of P3

1

/INT1 pin selected by 

bits 1 (I2

1

) and 2 (I2

2

) of register I2.

3: Count source is stopped by clearing to “0.”

Not available

Not available

Not available

Not available

ORCLK

Q

R

S

W1

0

1

0

I1

0

0

1

I1

1

P3

0

/INT0

1/4

1/16

1

0

W1

2

1

0

W1

3

MR

3

1

0

X

IN

Divistion circuit

(divided by 2)

Instruction clock

Internal clock 
generating circuit
(divided by 3)

Prescaler

0

1

I1

2

One-sided edge 
detection circuit

Both edges 
detection circuit

Q

R

S

W3

2

1

0

I2

0

0

1

I2

1

P3

1

/INT1

0

1

I2

2

One-sided edge 
detection circuit

Both edges 
detection circuit

(Note 1)

(Note 2)

Falling

Rising

Falling

Rising