Jameco Electronics 2000 ユーザーズマニュアル

The receiver and transmitter share the same interrupt vector, but it is possible to make the 
receive and transmit interrupt service routines (ISRs) separate by dispatching the interrupt 
to either of two different routines.  This is desirable to make the ISR less complex and to 
reduce the interrupt off time.  No interrupts will be lost since distinct interrupt flip-flops 
exist for receive and transmit.  The dispatcher can test the receiver data register full bit to 
dispatch.  If this bit is on, the interrupt is dispatched for receive, otherwise for transmit.  
The receiver receives first consideration because it must be serviced attentively or data 
could be lost.

The dispatcher might look as follows.

The individual interrupts would assume that register AF has been saved and the status reg-
ister has been loaded into Register A.

The interrupt service routines can, as a matter of good practice and obtaining optimum 
performance, remove the cause of the interrupt and re-enable the interrupts as soon as pos-
sible.  This keeps the interrupt latency down and allows the fastest transmission speed on 
all serial ports.

All the serial ports will normally generate priority level 1 interrupts.  In exceptional circum-
stances, one or more serial ports can be configured to use a higher priority interrupt.  
There is an exception to be aware of when a serial port has to operate at an extremely high 
speed.  At 115,200 bps, the highest speed of a PC serial port, the interrupts must be serviced 
in 10 baud times, or 86 µs, in order not to lose the received characters.  If all six serial ports 
were operating at this receive speed, it would be necessary to service the interrupt in less 
than 21.5 µs to assure no lost characters.  In addition, the time taken by other interrupts of 
equal or higher priority would have to be considered.  A receiver service routine might 
appear as follows below.  The byte at 

 is used to address the buffer where data bits 

are stored.  It is necessary to save and increment this byte because characters could be han-
dled out of order if two receiver interrupts take place in quick succession.