Motorola MCF5282 ユーザーズマニュアル
MOTOROLA
Chapter 8. System Control Module (SCM)
8-13
Internal Bus Arbitration
The initial state of the master priorities is M3 > M2 > M1 > M0. System software should
guarantee that the programmed Mn_PRTY fields are unique, otherwise the hardware
defaults to the initial-state priorities.
guarantee that the programmed Mn_PRTY fields are unique, otherwise the hardware
defaults to the initial-state priorities.
Table 8-7. MPARK Field Description
Bits
Name
Description
31–26
—
Reserved, should be cleared.
25
M2_P_EN
DMA bandwith control enable
0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
24
BCR24BIT
Enables the use of 24 bit byte count registers in the DMA module
0 DMA BCRs function as 16 bit counters.
1 DMA BCRs function as 24 bit counters.
0 DMA BCRs function as 16 bit counters.
1 DMA BCRs function as 24 bit counters.
23–22
M3_PRTY
Master priority level for master 3 (Fast Ethernet Controller)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
21–20
M2_PRTY
Master priority level for master 2 (DMA Controller)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
19–18
M0_PRTY
Master priority level for master 0 (ColdFire Core)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
17–16
M1_PRTY
Master priority level for master 1 (Not used in user mode)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
15
—
Reserved, should be cleared.
14
FIXED
Fixed or round robin arbitration
0 round robin arbitration
1 fixed arbitration
0 round robin arbitration
1 fixed arbitration
13
TIMEOUT
Timeout Enable
0 disable count for when a master is locked out by other masters.
1 enable count for when a master is locked out by other masters and allow access when
0 disable count for when a master is locked out by other masters.
1 enable count for when a master is locked out by other masters and allow access when
LCKOUT_TIME is reached.
12
PRKLAST
Park on the last active master or highest priority master if no masters are active
0 park on last active master
1 park on highest priority master
0 park on last active master
1 park on highest priority master
11–8
LCKOUT_TIME Lock-out Time. Lock-out time for a master being denied the bus.
The lock out time is defined as 2^ LCKOUT_TIME[3:0].
7–0
—
Reserved, should be cleared.