Motorola MCF5282 ユーザーズマニュアル

10-8

MOTOROLA

 

10.3.2 Interrupt Mask Register (IMRHn, IMRLn)

The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each
interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the request).
The IMRn is set to all ones by reset, disabling all interrupt requests. The IMRn can be read
and written. A write that sets bit 0 of the IMR forces the other 63 bits to be set, disabling
all interrupt sources, and providing a global mask-all capability.

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31

16

Field

INT_MASK[63:48]

Reset

1111_1111_1111_1111

R/W

R/W

15

0

Field

INT_MASK[47:32]

Reset

1111_1111_1111_1111

R/W

R/W

IPSBAR + 0xC08, 0xD08

Figure 10-3. Interrupt Mask Register High (IMRHn)

Table 10-6. IMRHn Field Descriptions 

31–0

INT_MASK

Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRHn bit 
determines whether an interrupt condition can generate an interrupt. The corresponding 
IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set.
0  The corresponding interrupt source is not masked
1  The corresponding interrupt source is masked

31

16

Field

INT_MASK[31:16]

Reset

1111_1111_1111_1111

R/W

R/W

15

1

0

Field

INT_MASK[16:1]

MASKALL

Reset

1111_1111_1111_1111

R/W

R/W

IPSBAR + 0xC0C, 0xD0C

Figure 10-4. Interrupt Mask Register Low (IMRLn)