Motorola MCF5282 ユーザーズマニュアル
16-10
MCF5282 User’s Manual
MOTOROLA
DMA Controller Module Programming Model
16.4.5 DMA Status Registers (DSR0–DSR3)
In response to an event, the DMA controller writes to the appropriate DSRn bit,
Figure 16-9. Only a write to DSRn[DONE] results in action.
Figure 16-9. Only a write to DSRn[DONE] results in action.
Table 16-4 describes DSRn fields.
15
AT
AT is available only if MPARK[BCR24BIT] = 1.
DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer or only
the final transfer.
0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the result of
DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer or only
the final transfer.
0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the result of
an external request.
1 Final transfer (when BCR reaches zero). For dual-address transfer, the acknowledge information is displayed
for both the read and write cycles.
14–0
—
Reserved, should be cleared.
7
6
5
4
3
2
1
0
Field
—
CE
BES
BED
—
REQ
BSY
DONE
Reset
0000_0000
R/W
R/W
Address
IPSBAR + 0x110, 0x150, 0x190, 0x1D0
Figure 16-9. DMA Status Registers (DSRn)
Table 16-4. DSRn Field Descriptions
Bits
Name
Description
7
—
Reserved, should be cleared.
6
CE
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR
= 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
= 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
5
BES
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
4
BED
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
3
—
Reserved, should be cleared.
2
REQ
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
Table 16-3. DCRn Field Descriptions (continued)
Bits
Name
Description