Motorola MCF5282 ユーザーズマニュアル

17-20

MOTOROLA

 

When the receive frame length exceeds 2047 bytes the frame is truncated and the TR bit is
set in the receive BD.

This section gives an overview of the registers, followed by a description of the buffers.

The FEC is programmed by a combination of control/status registers (CSRs) and buffer
descriptors. The CSRs are used for mode control and to extract global status information.
The descriptors are used to pass data buffers and related buffer information between the
hardware and software.

The FEC implementation requires a 1-Kbyte memory map space. This is divided into 2
sections of 512 bytes each. The first is used for control/status registers. The second contains
event/statistic counters held in the MIB block. Table 17-9 defines the top level memory
map.

Table 17-10 shows the FEC register memory map with each register address, name, and a
brief description.

IPSBAR + 0x1000-11FF

Control/Status Registers

IPSBAR + 0x1200-13FF

MIB Block Counters

0x1004

EIR

32

Interrupt Event Register

0x1008

EIMR

32

Interrupt Mask Register

0x1010

RDAR

32

Receive Descriptor Active Register

0x1014

TDAR

32

Transmit Descriptor Active Register

0x1024

ECR

32

Ethernet Control Register

0x1040

MDATA

32

MII Data Register

0x1044

MSCR

32

MII Speed Control Register

0x1064

MIBC

32

MIB Control/Status Register