Motorola MCF5282 ユーザーズマニュアル
MOTOROLA
Chapter 17. Fast Ethernet Controller (FEC)
17-41
Programming Model
17.5.4.19 FIFO Receive Bound Register (FRBR)
The FRBR is an 8-bit register that the user can read to determine the upper address bound
of the FIFO RAM. Drivers can use this value, along with the FRSR to appropriately divide
the available FIFO RAM between the transmit and receive data paths.
of the FIFO RAM. Drivers can use this value, along with the FRSR to appropriately divide
the available FIFO RAM between the transmit and receive data paths.
Table 17-30. TFWR Field Descriptions
Bits
Name
Descriptions
31–2
—
Reserved, should be cleared.
1–0
X_WMRK
Number of bytes written to transmit FIFO before transmission
of a frame begins
0x 64 bytes written
10 128 bytes written
11 192 bytes written
of a frame begins
0x 64 bytes written
10 128 bytes written
11 192 bytes written
31
16
Field
—
Reset
0000_0000_0000_0000
R/W
Read Only
15
10
9
2
1
0
Field
—
R_BOUND
—
Reset
0000_0110_0000_0000
R/W
Read Only
Address
IPSBAR + 0x114C
Figure 17-22. FIFO Receive Bound Register (FRBR)
Table 17-31. FRBR Field Descriptions
Bits
Name
Descriptions
31–10
—
Reserved, read as 0 (except bit 10, which is read as 1).
9–2
R_BOUND
Read-only. Highest valid FIFO RAM address.
1–0
—
Reserved, should be cleared.