Motorola MCF5282 ユーザーズマニュアル

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Chapter 23.  UART Modules  

23-17

Figure 23-16 shows both the external and internal signal groups.

An internal interrupt request signal (IRQ) is provided to notify the interrupt controller of an
interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt
level of a UART module is programmed in the interrupt controller.

The interrupt level and priority is programmed in the interrupt controller

—

ICR13 for

UART0, ICR14 for UART1, and ICR15 for UART2. See Section 10.3.6, “Interrupt Control
Register (ICRnx, (x = 1, 2,..., 63)).” 

Note that the UARTs can also be configured to automatically transfer data by using the
DMA rather than interrupting the core. When the FIFO has data on the receive path, a DMA
request can be issued. For more information on generating DMA requests, refer to
Section 23.5.6.1.2, “Setting up the UART to Request DMA Service,” and Section 16.2,
“DMA Request Control (DMAREQC).”

Table 23-12 briefly describes the UART module signals. 

The terms ‘assertion’ and ‘negation’ are used to avoid
confusion between active-low and active-high signals.
‘Asserted’ indicates that a signal is active, independent of the
voltage level; ‘negated’ indicates that a signal is inactive.

Internal

Four-Character

Receive Buffer

Two-Character

Transmit Buffer

Input Port

Output Port

 Interface

UART Module

Address Bus

Control

UCTS

URTS

URXD

UTXD

Control

Logic

or

Internal Bus

Data

to CPU

IRQ

To Interrupt

Controller

External

Interface

Signals

System Clock

Clock Source

Generator

or DMA

External Clock (DTIN)