Motorola MCF5282 ユーザーズマニュアル

23-30

MOTOROLA

 

Although the UART receive buffer is quadruple-buffered, the receiver shift register is still
shifting its characters when the DMA request is ready to read its contents; therefore, the
maximum number of data bytes read during a UART DMA request transfer is three.

When the DMA is configured for cycle steal, only one character will be transferred on a
DMA request. This mode should be used for DMA requests on FIFO not empty. DMA
requests are negated when a data byte is read from the UART receive buffer.

The UART can be configured to request service from the DMA controller on a FIFO FULL
of RxRDY condition. The steps needed to intialize DMA requests from the UART are listed
below.

1. Mask appropriate bits in IMR (bits 13-15 for UART0-UART2 respectively)
2. Initialize DMAREQC to map UART DMA Request to a DMA channel
3. Initialize DMA request in UART, see Table 23-14 

Table 23-15 shows the UART module initialization sequence.

UMR1x

6

RxIRQ.
0  DMA request on RxRDY
1  DMA request on FIFO full

UIMRx

1

RxFIFO full will enable DMA requests

UCRn

Reset the receiver and transmitter.
Reset the mode pointer (MISC[2–0] = 0b001).

UIVRn

Program the vector number for a UART module interrupt.

UIMRn

Enable the preferred interrupt sources.

UACRn

Initialize the input enable control (IEC bit).

UCSRn

Select the receiver and transmitter clock. Use timer as source if required.

UMR1n

If preferred, program operation of receiver ready-to-send (RxRTS bit).
Select receiver-ready or FIFO-full notification (RxRDY/FFULL bit).
Select character or block error mode (ERR bit).
Select parity mode and type (PM and PT bits).
Select number of bits per character (B/Cx bits).

UMR2n

Select the mode of operation (CMx bits).
If preferred, program operation of transmitter ready-to-send (TxRTS).
If preferred, program operation of clear-to-send (TxCTS bit).
Select stop-bit length (SBx bits).

UCR