Motorola MCF5282 ユーザーズマニュアル
lii
MCF5282 User’s Manual
MOTOROLA
Revision History
Revision History
Table iii. Revision History
Revision
Number
Date of
Release
Substantive Changes
Section/Page
0
11/2002
Preliminary release.
0.1
1/2003
Changed title from “MCF5282 ColdFire
®
Integrated Microprocessor User’s
Manual” to “MCF5282 ColdFire
®
Microcontroller User’s Manual.”
Title page
Added “This product incorporates SuperFlash® technology licensed from
SST.”
SST.”
Changed equation in footnote to f
sys
= f
ref
× 2(MFD + 2)/2 exp RFD; f
ref
×
2(MFD + 2)
≤ 80 MHz, f
sys
≤ 66 MHz.
Multiplied all PLL frequencies in table by 2.
Changed DTMRx to DTIMx.
Changed bit numbers from 63–32 to 31–0.
Changed bit numbers from 63–32 to 31–0.
Changed bit numbers from 63–32 to 31–0.
Added “Unlike the MCF5272, the MCF5282 does not have an independent
SDRAM clock signal. For the MCF5282, the timing of the SDRAM
controller is controlled by the CLKOUT signal.”
SDRAM clock signal. For the MCF5282, the timing of the SDRAM
controller is controlled by the CLKOUT signal.”
Added “Note: Because the MCF5282 has 24 external address lines, the
maximum SDRAM address size is 128 Mbits.”
maximum SDRAM address size is 128 Mbits.”
Changed reset value to 0010_0000_0000_0000.
Changed “PSTCLK” references to “CLKOUT.”
Changed “TEA” to “TA.”
Changed “RAS0” and “RAS1” to “SDRAM_CS0” and “SDRAM_CS1.”
Changed max input high voltage to 5.25 V.
Changed “System Integration Module” to “System Control Module.”
Appendix A
1
4/2003
Replaced Figure 6-1 with a more accurate block diagram.
Enhanced discussion of Flash blocks.
Added “Note:
Enabling Flash security will disable BDM
communications.”
Added “Note:
When Flash security is enabled, the chip will boot in
single chip mode regardless of the external reset configuration.”