Motorola MCF5282 ユーザーズマニュアル

25-20

MOTOROLA

 

interrupt routine can be fixed at compilation time. Each of the buffers is assigned a bit in
the IFLAG register. The bit is set when the corresponding buffer completes a successful
transmission or reception, and cleared when the CPU reads the interrupt flag register
(IFLAG) while the associated bit is set, and then writes it back as ‘1’ (and no new event of
the same type occurs between the read and the write actions).

The other 3 interrupt sources (Bus-off, Error and Wake-up) act in the same way, and are
located in the Error & Status register. The Bus-off and Error interrupt mask bits are located
in the CANCTRL0 register, and the Wake-up interrupt mask bit is located in the CANMCR.

This section describes the registers in the FlexCAN module. 

The FlexCAN has no hard-wired protection against invalid
bit/field programming within its registers. Specifically, no
protection is provided if the programming does not meet CAN
protocol requirements.

Programming the FlexCAN control registers is typically done during system initialization,
prior to the FlexCAN becoming synchronized with the CAN bus. The configuration
registers can be changed after synchronization by halting the FlexCAN module. This is
done when the user sets the HALT bit in the FlexCAN module configuration register
(CANMCR). The FlexCAN responds by setting the CANMCR[NOTRDY] bit.
Additionally, the control registers can be modified while the MCU is in background debug
mode.

Table 25-8 describes the CANMCR fields.

15

14

13

12

11

10

9

8

Field

STOP

FRZ

—

HALT

NOTRDY

WAKEMSK SOFTRST

FRZACK

Reset

0101_1001

R/W

R/W

7

6

5

4

3

0

Field

SUPV

SELFWAKE

APS

STOPACK

—

Reset

1000_0000

R/W

R/W

Address

IPSBAR + 0x1C_0000