Motorola MCF5282 ユーザーズマニュアル
MOTOROLA
Chapter 29. Debug Support
29-19
Background Debug Mode (BDM)
NOTE:
A not-ready response can be ignored except during a
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
29.5.2.1 Receive Packet Format
The basic receive packet, Figure 29-13, consists of 16 data bits and 1 status bit
.
29.5.2.2 Transmit Packet Format
The basic transmit packet, Figure 29-14, consists of 16 data bits and 1 control bit.
16
15
0
S
Data Field [15:0]
Figure 29-13. Receive BDM Packet
Table 29-15. Receive BDM Packet Field Description
Bits
Name
Description
16
S
Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored
unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer
after 32 processor clock periods.
S
unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer
after 32 processor clock periods.
S
Data
Message
0
xxxx
Valid data transfer
0
0xFFFF
Status OK
1
0x0000
Not ready with response; come again
1
0x0001
Error—Terminated bus cycle; data invalid
1
0xFFFF
Illegal command
15–0
D
Data. Contains the message to be sent from the debug module to the development system. The response
message is always a single word, with the data field encoded as shown above.
message is always a single word, with the data field encoded as shown above.
16
15
0
C
D
Figure 29-14. Transmit BDM Packet
Table 29-16. Transmit BDM Packet Field Description
Bits
Name
Description
16
C
Control. This bit is reserved. Command and data transfers initiated by the development system should clear C.
15–0
D
Data bits 15–0. Contains the data to be sent from the development system to the debug module.