Motorola MCF5282 ユーザーズマニュアル

MOTOROLA

Chapter 30.  Chip Configuration Module (CCM)  

30-11

 

During reset, certain module configurations depend on whether emulation mode is active
as determined by the state of the internal emulation signal.

During reset configuration, the CS0 chip select pin is optionally configured to select an
external boot device. In this case, the V (valid) bit in the CSMR0 register is ignored, and
CS0 is enabled after reset. CS0 is asserted for the initial boot fetch accessed from address
0x0000_0000 for the Stack Pointer and address 0x0000_0004 for the program counter
(PC). It is assumed that the reset vector loaded from address 0x0000_0004 causes the CPU
to start executing from external memory space decoded by CS0.

Output pad strength is determined during reset configuration as shown in Table 30-12.
Once reset is exited, the output pad strength configuration can be changed by programming
the LOAD bit of the chip configuration register.

 

The clock mode is selected during reset and reflected in the PLLMODE, PLLSEL, and
PLLREF bits of SYNSR. Once reset is exited, the clock mode cannot be changed.

Table 30-13 summarizes clock mode selection during reset configuration.

1

Modifying the default configurations is possible only if the external RCON pin is asserted low.

Master mode

D26 driven high

D17 driven high

D16 driven high

Single-chip mode

D26 driven high

D17 driven high

D16 driven low

Reserved

D26 driven high

D17 driven low

D16 driven high

Reserved

D26 driven low

D17 don’t care

D16 don’t care

1

Modifying the default configurations is possible only if the external RCON pin is asserted low.

Output pads configured for partial strength

D21 driven low

Output pads configured for full strength

D21 driven high