Motorola MCF5282 ユーザーズマニュアル

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Chapter 33.  Electrical Characteristics  

33-9

The Flash memory characteristics are shown in Table 33-8 and Table 33-9.

(V

DDH

 and V

DDA

 = 5.0 V

dc

 

±

 0.5V, V

DD

= 2.7-3.6V

, 

V

SS

 and V

SSA

= 0 V

dc

, V

RH

 – V

RL

 = 5 V

dc

 ± 0.5V, T

A

 within operating 

temperature range, f

sys

 = 16 MHz)

1

QADC Clock (QCLK) Frequency

1

1

Conversion characteristics vary with F

QCLK

 rate. Reduced conversion accuracy occurs at max F

QCLK

 rate. Using the 

QADC pins as GPIO functions during conversions may result in degraded results. Best QADC conversion accuracy is 
achieved at a frequency of 2 MHz. 

F

QCLK

0.5

2.1

MHz

2

Conversion Cycles

CC

14

28

QCLK 

cycles

3

Conversion Time
F

QCLK

 = 2.0 MHz

1

Min = CCW/IST =%00
Max = CCW/IST =%11

T

CONV

7.0

14.0

µ

s

4

Stop Mode Recovery Time

T

SR

—

10

µ

s

5

Resolution

2

2

At V

RH

 – V

RL

 = 5.12 V, one count = 5 mV

—

5

—

mV

6

Absolute (total unadjusted) error

 3, 4, 5

F

QCLK

 = 2.0 MHz 

2

, 2 clock input sample time

3

Accuracy tested and guaranteed at V

RH

 – V

RL

 = 5.0V ± 0.5V

4

Current Coupling Ratio, K, is defined as the ratio of the output current, I

out

, measured on the pin under test to the 

injection current, I

inj

, when both adjacent pins are overstressed with the specified injection current. K = I

out

/I

inj

. The 

input voltage error on the channel under test is calculated as Verr = I

inj

 

*

 K 

*

 R

S

.

5

Performance expected with production silicon.

AE

-2

2

Counts

7

Absolute (total unadjusted) error

 3, 4, 5

F

QCLK

 = 2.0 MHz 

2

, 2 clock input sample time

—

-3

3

Counts

(V

DDF

 = 2.7 to 3.6 V, T

A

 = T

L

 to T

H

)

1

1

T

L

 is defined to be –40°C and T

H

 is defined to be 85°C

System clock (read only)

f

sys(R)

0

—

80

MHz

System clock (program/erase)

2

2

Refer to the Flash section for more information

f

sys(P/E)

0.15

—

80

MHz