Motorola MCF5282 ユーザーズマニュアル
MOTOROLA
Chapter 33. Electrical Characteristics
33-25
JTAG and Boundary Scan Timing
33.15 JTAG and Boundary Scan Timing
Figure 33-15. Test Clock Input Timing
Table 33-23. JTAG and Boundary Scan Timing
Num
Characteristics
1
1
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing
Symbol
Min
Max
Unit
1
TCLK Frequency of Operation
f
JCYC
DC
1/4
f
sys
2
TCLK Cycle Period
t
JCYC
4
—
t
CYC
3
TCLK Clock Pulse Width
t
JCW
25.0
—
ns
4
TCLK Rise and Fall Times
t
JCRF
0.0
3.0
ns
5
Boundary Scan Input Data Setup Time to TCLK Rise
t
BSDST
5.0
—
ns
6
Boundary Scan Input Data Hold Time after TCLK Rise
t
BSDHT
25.0
—
ns
7
TCLK Low to Boundary Scan Output Data Valid
t
BSDV
0.0
30.0
ns
8
TCLK Low to Boundary Scan Output High Z
t
BSDZ
0.0
30.0
ns
9
TMS, TDI Input Data Setup Time to TCLK Rise
t
TAPBST
5.0
—
ns
10
TMS, TDI Input Data Hold Time after TCLK Rise
t
TAPBHT
10.0
—
ns
11
TCLK Low to TDO Data Valid
t
TDODV
0.0
25.0
ns
12
TCLK Low to TDO High Z
t
TDODZ
0.0
8.0
ns
13
TRST Assert Time
t
TRSTAT
100.0
—
ns
14
TRST Setup Time (Negation) to TCLK High
t
TRSTST
10.0
—
ns
TCLK
V
IL
V
IH
3
3
4
4
2
(input)