Motorola MVME172 ユーザーズマニュアル
Programming Model
http://www.mcg.mot.com/literature
3-27
3
DRAM/SRAM Options Register
Note that this register is read only and is initialized at reset.
DZ2-DZ0 DZx bits indicate the size and architecture of the non-ECC
DRAM array. Software must initialize the DRAM Space
Size Register ($FFF42024 bits 26 - 24) based on the value
of DZ2 - DZ0. DZ2 - DZ0 are initialized at reset to a value
which is determined by the contents of a factory-
programmed resident device.
Size Register ($FFF42024 bits 26 - 24) based on the value
of DZ2 - DZ0. DZ2 - DZ0 are initialized at reset to a value
which is determined by the contents of a factory-
programmed resident device.
SZ1-SZ0
SZx bits indicate the size of the SRAM array. Software
must initialize the SRAM Space Size Register
($FFF42024 bits 9 - 8) based on the value of SZ1 - SZ0.
must initialize the SRAM Space Size Register
($FFF42024 bits 9 - 8) based on the value of SZ1 - SZ0.
Table 3-4. DRAM Size Control Bit Encoding
DZ2 - DZ0
Memory Size
$0
Not defined for MVME172
$1
Not defined for MVME172
$2
Not defined for MVME172
$3
Not defined for MVME172
$4
4 MByte (non-interleaved)
$5
8 MByte (non-interleaved)
$6
DRAM is not present.
$7
16 MByte (interleaved)
ADR/SIZ
$FFF42024 (8 bits)
BIT
23
22
21
20
19
18
17
16
NAME
F0
SZ1
SZ0
DZ2
DZ1
DZ0
OPER
R
R
R
R
R
R
R
R
RESET
Application Specific