Motorola MVME172 ユーザーズマニュアル
3-30
Computer Group Literature Center Web Site
MC2 Chip
3
LANC Error Status Register
SCLR
Writing a 1 to this bit clears bits LTO, EXT, and PRTY.
Reading this bit always yields 0.
Reading this bit always yields 0.
LTO, EXT, PRTY
These bits indicate the status of the last local bus error
condition encountered by the LANC while performing
DMA accesses to the local bus. A local bus error
condition is flagged by the assertion of TEA*. When the
LANC receives TEA* if the source of the error is local
time-out, then LTO is set and EXT and PRTY are cleared.
If the source of the TEA* is due to an error in going to the
VMEbus, then EXT is set and the other two status bits are
cleared. If the source of the error is DRAM parity check
error, then PRTY is set and the other two status bits are
cleared. If the source of the error is none of the above
conditions, then all three bits are cleared. Writing a 1 to bit
24 (SCLR) also clears all three bits.
condition encountered by the LANC while performing
DMA accesses to the local bus. A local bus error
condition is flagged by the assertion of TEA*. When the
LANC receives TEA* if the source of the error is local
time-out, then LTO is set and EXT and PRTY are cleared.
If the source of the TEA* is due to an error in going to the
VMEbus, then EXT is set and the other two status bits are
cleared. If the source of the error is DRAM parity check
error, then PRTY is set and the other two status bits are
cleared. If the source of the error is none of the above
conditions, then all three bits are cleared. Writing a 1 to bit
24 (SCLR) also clears all three bits.
ADR/SIZ
$FFF42028 (8 bits)
BIT
31
30
29
28
27
26
25
24
NAME
PRTY
EXT
LTO
SCLR
OPER
R
R
R
R
R
R
R
C
RESET
0
0
0
0
0 PL
0 PL
0 PL
0 PL