Motorola MVME172 ユーザーズマニュアル
Functional Description
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Programmable Clock
The IP2 chip implements a general purpose programmable clock output for
external connection to the IndustryPacks. This feature complies with the
STROBE function defined in the IndustryPack specification. The
programmable clock’s clock source is the MC68060 bus clock. This clock
input is fed through an 8-bit programmable pre-scaling counter whose
output is fed to a 16-bit counter. The 16-bit counter increments at rising
edges of the output of the pre-scale logic and clears every time it reaches
the value programmed into the 16-bit programmable timer register.
Depending on its programmed mode, the programmable clock output
either pulses or toggles each time the 16-bit counter matches and clears.
Additional control bits in the programmable clock control register allow
software to stop, start, clear, and reverse the polarity of the programmable
clock output. The programmable clock output’s programmable frequency
range is from approximately 4 Hz to 16 MHz. The programmable clock
logic also includes local bus interrupt control.
external connection to the IndustryPacks. This feature complies with the
STROBE function defined in the IndustryPack specification. The
programmable clock’s clock source is the MC68060 bus clock. This clock
input is fed through an 8-bit programmable pre-scaling counter whose
output is fed to a 16-bit counter. The 16-bit counter increments at rising
edges of the output of the pre-scale logic and clears every time it reaches
the value programmed into the 16-bit programmable timer register.
Depending on its programmed mode, the programmable clock output
either pulses or toggles each time the 16-bit counter matches and clears.
Additional control bits in the programmable clock control register allow
software to stop, start, clear, and reverse the polarity of the programmable
clock output. The programmable clock output’s programmable frequency
range is from approximately 4 Hz to 16 MHz. The programmable clock
logic also includes local bus interrupt control.
Error Reporting
The following paragraphs describe the IP2 chip error reporting.
Error Reporting as a Local Bus Slave
The IP2 chip does not have the ability to assert the TEA* signal as a local
bus slave. Because of this, the only bus error cycles that should ever be
encountered when accessing to or through the IP2 chip are those that come
from an external local bus timer due to no response from an IndustryPack.
Note that any external local bus timer should be set for no less than 5
microseconds to allow for normal accesses to the slowest IndustryPack.
bus slave. Because of this, the only bus error cycles that should ever be
encountered when accessing to or through the IP2 chip are those that come
from an external local bus timer due to no response from an IndustryPack.
Note that any external local bus timer should be set for no less than 5
microseconds to allow for normal accesses to the slowest IndustryPack.
Error Reporting as a Local Bus Master
The IP2 chip does not connect to the ST1 and ST0 signal lines.
Consequently, when it receives a TEA* termination to any cycle for which
it is local bus master, no status will be available to indicate the source of
the bus error. There is a status bit in each DMAC status register which
Consequently, when it receives a TEA* termination to any cycle for which
it is local bus master, no status will be available to indicate the source of
the bus error. There is a status bit in each DMAC status register which