Motorola MVME172 ユーザーズマニュアル
Programming Model
http://www.mcg.mot.com/literature
5-17
5
Dummy Register 1
Dummy Register 1 is hard-wired to all zeros. Writes to this register are
ignored; however, the MCECC always terminates the cycles properly with
TA*.
ignored; however, the MCECC always terminates the cycles properly with
TA*.
Difference from MEMC040: register = Alternate Control
for MEMC040; register = $00 for MCECC.
for MEMC040; register = $00 for MCECC.
Base Address Register
These eight bits are combined with the two most significant bits in Register
7 (the next register) to form BAD31-BAD22, which defines the base
address of the memory. For larger memory sizes, the lower significant bits
are ignored.
7 (the next register) to form BAD31-BAD22, which defines the base
address of the memory. For larger memory sizes, the lower significant bits
are ignored.
Difference from MEMC040: none.
The bit assignments for the Base Address Register are:
ADR/SIZ
1st $FFF43010/2nd $FFF43110 (8-bits)
BIT
31
30
29
28
27
26
25
24
NAME
0
0
0
0
0
0
0
0
OPER
R
R
R
R
R
R
R
R
RESET
X
X
X
X
X
X
X
X
ADR/SIZ
1st $FFF43014/2nd $FFF43114 (8-bits)
BIT
31
30
29
28
27
26
25
24
NAME
BAD31
BAD30
BAD29
BAD28
BAD27
BAD26
BAD25
BAD24
OPER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS