Motorola MVME172 ユーザーズマニュアル
1-52
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Board Description and Memory Maps
1
Status:
Bit 7 of the MPU Status and DMA Interrupt Count Register, (actually in
the DMAC Status Register) at address $FFF40048.
Bit 7 of the MPU Status and DMA Interrupt Count Register, (actually in
the DMAC Status Register) at address $FFF40048.
Comments:
The local bus timer timed out. This usually indicates the MPU tried to
read or write an address at which there was no resource. Otherwise, it
indicates a hardware problem.
The local bus timer timed out. This usually indicates the MPU tried to
read or write an address at which there was no resource. Otherwise, it
indicates a hardware problem.
DMAC VMEbus Error
Description:
The DMAC experienced a VMEbus error during an attempted transfer.
The DMAC experienced a VMEbus error during an attempted transfer.
MPU Notification:
DMAC interrupt (when enabled).
DMAC interrupt (when enabled).
Status:
The VME bit is set in the DMAC Status Register (address $FFF40048 bit
1).
The VME bit is set in the DMAC Status Register (address $FFF40048 bit
1).
Comments:
This indicates the DMAC attempted to access a VMEbus address at which
there was no resource or the VMEbus slave returned a BERR signal.
This indicates the DMAC attempted to access a VMEbus address at which
there was no resource or the VMEbus slave returned a BERR signal.
DMAC Parity Error
Note
The 400/500-Series MVME172 models do not contain parity
DRAM.
DRAM.
Description:
Parity error while the DMAC was reading DRAM.
Parity error while the DMAC was reading DRAM.
MPU Notification:
DMAC interrupt (when enabled).
DMAC interrupt (when enabled).
Status:
The DLPE bit is set in the DMAC Status Register (address $FFF40048 bit
5).
The DLPE bit is set in the DMAC Status Register (address $FFF40048 bit
5).