Motorola MVME172 ユーザーズマニュアル
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VMEchip2
2
The DMAC also supports command chaining through the use of a singly-
linked list built in local memory. Each entry in the list includes a VMEbus
address, a local bus address, a byte count, a control word, and a pointer to
the next entry. When the command chaining mode is enabled, the DMAC
reads and executes commands from the list in local memory until all
commands are executed.
linked list built in local memory. Each entry in the list includes a VMEbus
address, a local bus address, a byte count, a control word, and a pointer to
the next entry. When the command chaining mode is enabled, the DMAC
reads and executes commands from the list in local memory until all
commands are executed.
The DMAC can be programmed to send an interrupt request to the local
bus interrupter when any specific table entry has completed. In addition the
DMAC always sends an interrupt request at the normal completion of a
request or when an error is detected. If the DMAC interrupt is enabled in
the DMAC, the local bus is interrupted.
bus interrupter when any specific table entry has completed. In addition the
DMAC always sends an interrupt request at the normal completion of a
request or when an error is detected. If the DMAC interrupt is enabled in
the DMAC, the local bus is interrupted.
To allow increased flexibility in managing the bus tenure to optimize bus
usage as required by the system configuration, the chip contains control
bits that allow the DMAC time on and off the bus to be programmed. Using
these control bits, software can instruct the DMA Controller to acquire the
bus, maintain mastership for a specific amount of time, and then, after
relinquishing it, refrain from requesting it for another specific amount of
time.
usage as required by the system configuration, the chip contains control
bits that allow the DMAC time on and off the bus to be programmed. Using
these control bits, software can instruct the DMA Controller to acquire the
bus, maintain mastership for a specific amount of time, and then, after
relinquishing it, refrain from requesting it for another specific amount of
time.
No Address Increment DMA Transfers
During normal memory-to-memory DMA transfers, the DMA controller is
programmed to increment the local bus and VMEbus address. This allows
a block of data to be transferred between VMEbus memory and local bus
memory. In some applications, it may be desirable to transfer a block of
data from local bus memory to a single VMEbus address. This single
VMEbus address may be a FIFO or similar type device which can accept
a large amount of data but only appears at single VMEbus address. The
DMA controller provides support for these devices by allowing transfers
without incrementing the VMEbus address. The DMA controller also
allows DMA transfers without incrementing the local bus address,
however the MVME172 does not have any onboard devices that benefit
from not incrementing the local bus address.
programmed to increment the local bus and VMEbus address. This allows
a block of data to be transferred between VMEbus memory and local bus
memory. In some applications, it may be desirable to transfer a block of
data from local bus memory to a single VMEbus address. This single
VMEbus address may be a FIFO or similar type device which can accept
a large amount of data but only appears at single VMEbus address. The
DMA controller provides support for these devices by allowing transfers
without incrementing the VMEbus address. The DMA controller also
allows DMA transfers without incrementing the local bus address,
however the MVME172 does not have any onboard devices that benefit
from not incrementing the local bus address.
The transfer mode on the VMEbus may be D16, D16/BLT, D32, D32/BLT
or D64/BLT. When the no increment address mode is selected, some of the
VMEbus address lines and local bus address lines continue to increment in
some modes. This is required to support the various port sizes and to allow
or D64/BLT. When the no increment address mode is selected, some of the
VMEbus address lines and local bus address lines continue to increment in
some modes. This is required to support the various port sizes and to allow