Epson S1D13504 ユーザーズマニュアル
Page 94
Epson Research and Development
Vancouver Design Center
S1D13504
Hardware Functional Specification
X19A-A-002-18
Issue Date: 01/01/30
bit 7
HRTC Polarity Select
For CRTs, this bit selects the polarity of the HRTC. When this bit = 1, the HRTC pulse is active
high. When this bit = 0, the HRTC pulse is active low.
For CRTs, this bit selects the polarity of the HRTC. When this bit = 1, the HRTC pulse is active
high. When this bit = 0, the HRTC pulse is active low.
bit 6
FPLINE Polarity Select
This bit selects the polarity of the FPLINE for TFT and passive LCD. When this bit = 1, the
FPLINE pulse is active high for TFT and active low for passive LCD. When this bit = 0, the
FPLINE pulse is active low for TFT and active high for passive LCD.
This bit selects the polarity of the FPLINE for TFT and passive LCD. When this bit = 1, the
FPLINE pulse is active high for TFT and active low for passive LCD. When this bit = 0, the
FPLINE pulse is active low for TFT and active high for passive LCD.
bits 3-0
HRTC/FPLINE Pulse Width Bits [3:0]
For CRTs and TFTs, these bits specify the pulse width of HRTC and FPLINE respectively. For pas-
sive LCDs, FPLINE is automatically created and these bits have no effect.
For CRTs and TFTs, these bits specify the pulse width of HRTC and FPLINE respectively. For pas-
sive LCDs, FPLINE is automatically created and these bits have no effect.
HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1)
×
8.
The maximum HRTC pulse width is 128 pixels.
Note
This register must be programmed such that
(REG[05h] + 1)
(REG[05h] + 1)
≥
(REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
REG[08h] bits 7-0
Vertical Display Height Bits [9:0]
REG[09h] bits 1-0
These bits specify the LCD panel and/or the CRT vertical display height, in 1-line resolution. For a
dual LCD panel only configuration, this register should be programmed to half the panel size.
dual LCD panel only configuration, this register should be programmed to half the panel size.
Vertical display height in number of lines = (ContentsOfThisRegister) + 1.
The maximum vertical display height is 1024 lines.
The maximum vertical display height is 1024 lines.
HRTC/FPLINE Pulse Width Register
REG[07h]
RW
HRTC
Polarity
Select
Polarity
Select
FPLINE
Polarity
Select
Polarity
Select
n/a
n/a
HRTC/
FPLINE Pulse
Width Bit 3
FPLINE Pulse
Width Bit 3
HRTC/
FPLINE Pulse
Width Bit 2
FPLINE Pulse
Width Bit 2
HRTC/
FPLINE Pulse
Width Bit 1
FPLINE Pulse
Width Bit 1
HRTC/
FPLINE Pulse
Width Bit 0
FPLINE Pulse
Width Bit 0
Table 8-4: FPLINE Polarity Selection
FPLINE Polarity Select
Passive LCD FPLINE Polarity
TFT FPLINE Polarity
0
active high
active low
1
active low
active high
Vertical Display Height Register 0
REG[08h]
RW
Vertical
Display
Height Bit 7
Display
Height Bit 7
Vertical
Display
Height Bit 6
Display
Height Bit 6
Vertical
Display
Height Bit 5
Display
Height Bit 5
Vertical
Display
Height Bit 4
Display
Height Bit 4
Vertical
Display
Height Bit 3
Display
Height Bit 3
Vertical
Display
Height Bit 2
Display
Height Bit 2
Vertical
Display
Height Bit 1
Display
Height Bit 1
Vertical
Display
Height Bit 0
Display
Height Bit 0
Vertical Display Height Register 1
REG[09h]
RW
n/a
n/a
n/a
n/a
n/a
n/a
Vertical
Display
Height Bit 9
Display
Height Bit 9
Vertical
Display
Height Bit 8
Display
Height Bit 8