Epson S1D13504 ユーザーズマニュアル
Page 102
Epson Research and Development
Vancouver Design Center
S1D13504
Hardware Functional Specification
X19A-A-002-18
Issue Date: 01/01/30
8.2.6 Power Save Configuration Registers
bit 3
LCD Power Disable
When this bit = 1 the LCDPWR output is directly forced to the Off state. The LCDPWR “On/Off”
state is configured by MD10 at the rising edge of RESET#. When this bit = 0 the LCDPWR output
is controlled by the panel on/off sequencing logic. See Table 5-8: “Summary of Power On / Reset
Options,” on page 31.
When this bit = 1 the LCDPWR output is directly forced to the Off state. The LCDPWR “On/Off”
state is configured by MD10 at the rising edge of RESET#. When this bit = 0 the LCDPWR output
is controlled by the panel on/off sequencing logic. See Table 5-8: “Summary of Power On / Reset
Options,” on page 31.
bits 2-1
Suspend Refresh Select Bits [1:0]
These bits specify the type of DRAM refresh to use in Suspend mode.
These bits specify the type of DRAM refresh to use in Suspend mode.
Note
These bits should not be changed when suspend mode is enabled.
bit 0
Software Suspend Mode Enable
When this bit = 1 software suspend mode is enabled. When this bit = 0 software suspend mode is disabled.
When this bit = 1 software suspend mode is enabled. When this bit = 0 software suspend mode is disabled.
8.2.7 Miscellaneous Registers
bit 7
Host Interface Disable
This bit must be programmed to 0 to enable the Host Interface. This bit goes high on reset. When
this bit is high, all memory and all registers except REG[1Ah] (read-only), REG[28h] through
REG[2Fh], and REG[1Bh] are inaccessible.
This bit must be programmed to 0 to enable the Host Interface. This bit goes high on reset. When
this bit is high, all memory and all registers except REG[1Ah] (read-only), REG[28h] through
REG[2Fh], and REG[1Bh] are inaccessible.
Power Save Configuration Register
REG[1Ah]
RW
n/a
n/a
n/a
n/a
LCD Power
Disable
Disable
Suspend
Refresh
Select Bit 1
Refresh
Select Bit 1
Suspend
Refresh
Select Bit 0
Refresh
Select Bit 0
Software
Suspend
Mode Enable
Suspend
Mode Enable
Table 8-10: Suspend Refresh Selection
Suspend Refresh Select Bits [1:0]
DRAM Refresh Type
00
CBR Refresh
01
Self-Refresh
1x
No Refresh
Miscellaneous Disable Register
REG[1Bh]
RW
Host Interface
Disable
Disable
n/a
n/a
n/a
n/a
n/a
n/a
Half Frame
Buffer Disable
Buffer Disable