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Epson S1D13504 ユーザーズマニュアル

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Epson Research and Development
Page 119
Vancouver Design Center
Hardware Functional Specification
S1D13504
Issue Date: 01/01/30 
X19A-A-002-18
11  Clocking
11.1  Maximum MCLK: PCLK Ratios
Table 11-1: Maximum PCLK Frequency with EDO-DRAM
Display type
N
RC
Maximum PCLK Allowed
1 bpp
2 bpp
4 bpp
8 bpp
16 bpp
• Single Panel.
• CRT.
• Dual Monochrome/Color Panel with Half Frame Buffer 
Disabled.
• Simultaneous CRT + Single Panel.
• Simultaneous CRT + Dual Monochrome/Color Panel 
with Half Frame Buffer Disabled.
5, 4, 3
MCLK
• Dual Monochrome Panel with Half Frame Buffer 
Enabled.
• Simultaneous CRT + Dual Monochrome Panel with 
Half Frame Buffer Enable.
5
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/3
4
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/3
3
MCLK
MCLK
MCLK/2
MCLK/2
MCLK/2
• Dual Color Panel with Half Frame Buffer Enabled.
• Simultaneous CRT + Dual Color Panel with Half 
Frame Buffer Enable.
5
MCLK/2
MCLK/2
MCLK/2
MCLK/3
MCLK/3
4
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/3
3
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/3
Table 11-2: Maximum PCLK Frequency with FPM-DRAM
Display type
N
RC
Maximum PCLK allowed 
1 bpp
2 bpp
4 bpp
8 bpp
16 bpp
• Single Panel.
• CRT.
• Dual Monochrome/Color Panel with Half Frame Buffer 
Disabled.
• Simultaneous CRT + Single Panel.
• Simultaneous CRT + Dual Monochrome/Color Panel 
with Half Frame Buffer Disabled.
5, 4, 3
MCLK
• Dual Monochrome Panel with Half Frame Buffer 
Enabled.
• Simultaneous CRT + Dual Monochrome Panel with 
Half Frame Buffer Enable.
5
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/3
4
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/2
3
MCLK
MCLK
MCLK
MCLK/2
MCLK/2
• Dual Color Panel with Half Frame Buffer Enabled.
• Simultaneous CRT + Dual Color Panel with Half 
Frame Buffer Enable.
5
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/3
4
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/3
3
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/2