Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 129
Vancouver Design Center
Hardware Functional Specification
S1D13504
Issue Date: 01/01/30
X19A-A-002-18
13.3 Power Save Mode Function Summary
Note
(1) except for RAMDAC registers.
(2) Yes if CBR suspend mode refresh is selected.
(2) Yes if CBR suspend mode refresh is selected.
13.4 Pin States in Power Save Modes
Note
1. FPFRAME and FPLINE are forced to their inactive states as defined by REG[0Ch] bit 6
and REG[07h] bit 6 respectively.
2. Selectable: may be CBR refresh, self-refresh or no refresh at all.
3. DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled.
4. Active for non-DAC register access only.
3. DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled.
4. Active for non-DAC register access only.
Table 13-1: Power Save Mode Function Summary
Function
Power Save Mode (PSM)
Normal
(Active)
Software
Suspend
Suspend
Hardware
Suspend
Display Active?
Yes
No
No
Register Access Possible?
Yes
Yes (1)
No
Memory Access Possible?
Yes
No
No
Host Bus Interface Running?
Yes
Yes
No
Memory Interface Running?
Yes
No (2)
No (2)
Table 13-2: Pin States in Power Save Modes
Pins
Pin State
Normal
(Active)
Software
Suspend
Suspend
Hardware
Suspend
LCD outputs
Active
Forced Low (1)
Forced Low (1)
LCDPWR
On
Off
Off
DRAM outputs
Active
Refresh Only (2)
Refresh Only (2)
CRT / DAC outputs
Active
Disabled (3)
Disabled (3)
Host Interface outputs
Active
Active (4)
Disabled