Epson S1D13504 ユーザーズマニュアル
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Epson Research and Development
Vancouver Design Center
S1D13504
Interfacing to the NEC VR4102™ Microprocessor
X19A-G-007-07
Issue Date: 01/02/02
4 VR4102 to S1D13504 Interface
4.1 Hardware Description
The NEC V
R
4102
TM
microprocessor is specifically designed to support an external LCD
controller by providing the internal address decoding and control signals necessary. By
using this interface only minimal external “glue” logic is necessary.
using this interface only minimal external “glue” logic is necessary.
The diagram below shows a typical implementation of the VR4102 to S1D13504 interface.
Figure 4-1: Typical Implementation of VR4102 to S1D13504 Interface
Note
For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.
WE1#
WE0#
DB[15:0]
WAIT#
RD1#
RD0#
BUSCLK
S1D13504
CS#
M/R#
RESET#
AB[20:0]
A0
A0
A21
SHB#
WR#
DAT[15:0]
LCDCS#
RD#
BUSCLK
LCDRDY
ADD[25:0]
NEC V
R
4102
Pull-up
Notes: The propagation delay of the Read/write Decode Logic shown above must be less than 10 nsec.
Read/Write
Decode Logic
Decode Logic
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
System RESET