Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 39
Vancouver Design Center
Hardware Functional Specification
S1D13504
Issue Date: 01/01/30
X19A-A-002-18
1.
If the S1D13504 host interface is disabled, the timing for DTACK# driven high is relative to
the falling edge of AS# or the first positive edge of CLK after A[20:1] and M/R# become val-
id,
whichever occurs later.
the falling edge of AS# or the first positive edge of CLK after A[20:1] and M/R# become val-
id,
whichever occurs later.
2.
If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# become val-
id, whichever occurs later.
ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# become val-
id, whichever occurs later.
Table 7-2: MC68K Bus 1 Interface Timing
Symbol
Parameter
Min
Max
Units
t1
Clock period
30
ns
t2
Clock pulse width high
5
ns
t3
Clock pulse width low
5
ns
t4
A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and
either UDS#=0 or LDS# = 0
either UDS#=0 or LDS# = 0
4
ns
t5
A[20:1], M/R# hold from AS#
0
ns
t6
CS# hold from AS#
0
ns
t7
R/W# setup to before to either UDS#=0 or LDS# = 0
5
ns
t8
R/W# hold from AS#
0
ns
t9
1
AS# = 0 and CS# = 0 to DTACK# driven high
1
ns
t10
AS# high to DTACK# high impedance
1
5
ns
t11
D[15:0] valid to second CLK where CS# = 0 AS# = 0, and either
UDS#=0 or LDS# = 0 (write cycle)
UDS#=0 or LDS# = 0 (write cycle)
0
ns
t12
D[15:0] hold from falling edge of DTACK# (write cycle)
0
ns
t13
2
Falling edge of UDS#=0 or LDS# = 0 to D[15:0] driven (read
cycle)
cycle)
3
ns
t14
D[15:0] valid to DTACK# falling edge (read cycle)
0
ns
t15
UDS# and LDS# high to D[15:0] invalid/high impedance (read
cycle)
cycle)
2
11
ns
t16
AS# high setup to CLK
3
ns