Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 15
Vancouver Design Center
Interfacing to the Motorola MPC821 Microprocessor
S1D13504
Issue Date: 01/02/02
X19A-G-010-05
4 MPC821 to S1D13504 Interface
4.1 Hardware Description
The interface between the S1D13504 and the MPC821 requires no glue logic. All lines are
directly connected. A single resistor is used to speed up the rise time of the WAIT# (TA)
signal when terminating the bus cycle.
directly connected. A single resistor is used to speed up the rise time of the WAIT# (TA)
signal when terminating the bus cycle.
BS# (bus start) is not used in this implementation and should be tied low (connected to
GND).
GND).
The following diagram shows a typical implementation of the MPC821 to S1D13504
interface.
interface.
Figure 4-1: Typical Implementation of MPC821 to S1D13504 Interface
Note
For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping” .
MPC821
S1D13504
A[11:31]
D[0:15]
CS4
TA
WE0
WE1
OE
SYSCLK
AB[20:0]
DB[15:0]
CS#
WAIT#
WE1#
WE0#
RD1#
RD0#
BUSCLK
RESET#
Vcc
470
A10
M/R#
Note:
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
System RESET