Epson S1D13504 ユーザーズマニュアル

Epson Research and Development

Page 9

Vancouver Design Center

Interfacing to the PC Card Bus

S1D13504

Issue Date: 01/02/02

X19A-G-009-05

During a read cycle, OE# (output enable) is driven low. A write cycle is specified by
driving OE# high and driving the write enable signal (WE#) low. The cycle can be
lengthened by driving WAIT# low for the time needed to complete the cycle.

The figure below illustrates a typical memory read cycle on the PC Card bus.

Figure 2-1: PC Card Read Cycle

The figure below illustrates a typical memory write cycle on the PC Card bus.

Figure 2-2: PC Card Write Cycle

A[25:0]

CE1#

OE#

WAIT#

ADDRESS VALID

DATA VALID

Hi-Z

D[15:0]

REG#

CE2#

Transfer Start

Transfer Complete