Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 43
Vancouver Design Center
Hardware Functional Specification
S1D13504
Issue Date: 01/01/30
X19A-A-002-18
1.
If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the
falling edge of CS# and RD0#, RD1#, WE0#, WE1# or the first positive edge of BCLK after
A[20:0] and M/R# become valid, whichever occurs later.
falling edge of CS# and RD0#, RD1#, WE0#, WE1# or the first positive edge of BCLK after
A[20:0] and M/R# become valid, whichever occurs later.
2.
If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become
valid, whichever occurs later.
ing edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become
valid, whichever occurs later.
Table 7-4: Generic MPU Interface Synchronous Timing
Symbol
Parameter
Min
Max
Units
T
BCLK
Bus clock period
25
ns
t1
A[20:0], M/R#, CS#, RD0#,RD1#,WE0#,WE1# hold time
1
ns
t2
A[20:0], M/R#, CS#, RD0#,RD1#,WE0#,WE1# setup time
5
ns
t3
RD0#,RD1#,WE0#,WE1# high to A[20:0], M/R# invalid and CS# high
0
ns
t4
1
RD0#,RD1#,WE0#,WE1# low and CS# low to WAIT# driven low
1
7
ns
t5
BCLK to WAIT# high
0
15
ns
t6
RD0#,RD1#,WE0#,WE1# high to WAIT# high impedance
1
6
ns
t7
D[15:0] valid to second BCLK where RD0#,RD1#,WE0#,WE1# low and CS#
low (write cycle)
low (write cycle)
5
ns
t8
D[15:0] hold from WE0#, WE1# high (write cycle)
0
ns
t9
2
RD0#,RD1# low to D[15:0] driven (read cycle)
3
15
ns
t10
D[15:0] valid to WAIT# high (read cycle)
0
t11
RD0#, RD1# high to D[15:0] high impedance (read cycle)
2
10