Epson S1D13504 ユーザーズマニュアル
Page 60
Epson Research and Development
Vancouver Design Center
S1D13504
Hardware Functional Specification
X19A-A-002-18
Issue Date: 01/01/30
Table 7-14: FPM-DRAM Read-Write Timing
Symbol
Parameter
Min Typ
Max
Units
t1
Memory clock
40
ns
t2
Random read or write cycle time (REG[22h] bits [6:5] = 00)
5 t1
ns
Random read or write cycle time (REG[22h] bits [6:5] = 01)
4 t1
ns
Random read or write cycle time (REG[22h] bits [6:5] = 10)
3 t1
ns
t3
Row address setup time (REG[22h] bits [3:2] = 00)
2 t1
ns
Row address setup time (REG[22h] bits [3:2] = 01)
1.45 t1
ns
Row address setup time (REG[22h] bits [3:2] = 10)
1 t1
ns
t4
Row address hold time (REG[22h] bits [3:2] = 00 or 10)
t1 - 1
ns
Row address hold time (REG[22h] bits [3:2] = 01)
0.45 t1 - 1
ns
t5
Column address set-up time
0.45 t1 - 1
ns
t6
Column address hold time
0.45 t1 - 1
ns
t7
RAS# precharge time (REG[22h] bits [3:2] = 0)
2 t1 - 1
ns
RAS# precharge time (REG[22h] bits [3:2] = 01)
1.45 t1 - 1
ns
RAS# precharge time (REG[22h] bits [3:2] = 10)
1 t1 - 1
ns
t8
RAS# to CAS# delay time
(REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10)
(REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10)
1.45 t1 - 2
1.55 t1
ns
RAS# to CAS# delay time
(REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10)
(REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10)
2.45 t1 - 2
2.55 t1
ns
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 01)
1 t1 - 2
1 t1
ns
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01)
2 t1 - 2
2 t1
ns
t9
Read Data turn-off delay from CAS#
2
ns
t10
Write Data enable delay from WE#
0.45 t1
ns