Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 77
Vancouver Design Center
Hardware Functional Specification
S1D13504
Issue Date: 01/01/30
X19A-A-002-18
7.4.9 Dual Monochrome 8-Bit Panel Timing
Figure 7-31: Dual Monochrome 8-Bit Panel Timing
VDP
= Vertical Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
VNDP
= Vertical Non-Display Period
= (REG[0Ah] bits [5:0]) + 1
HDP
= Horizontal Display Period
= ((REG[04h] bits [6:0]) + 1)*8Ts
HNDP
= Horizontal Non-Display Period
= ((REG[05h] bits [4:0]) + 1)*8Ts
VDP
FPLINE
FPSHIFT
UD[3:0], LD[3:0]
FPFRAME
FPLINE
MOD
UD2
1-2
1-6
1-638
UD1
1-3
1-7
1-639
UD0
1-4
1-8
1-640
LD3
241-1
241-5
241-637
LD2
241-638
LD1
241-639
LD0
241-640
UD3
1-1
1-5
1-637
HDP
MOD
241-2
241-6
241-3
241-7
241-4
241-8
VNDP
HNDP
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242