Intel AS/400 RISC Server ユーザーズマニュアル
C.8.2 Model 810 and 825 iSeries for Domino (February 2003)
3100
380
0
1020
1
2 MB
540
810-2466 (7407)
4200
530
0
1470
1
4 MB
750
810-2467 (7410)
7900
950
0
2700
2
4 MB
750
810-2469 (7428)
11600
na
0
na
4
1.41 MB
1100
825-2473 (7416)
17400
2890
0
6600
6
1.41 MB
1100
825-2473 (7416)
MCU
Processor
CIW*
5250 OLTP
CPW*
Processor CPW
CPU
Range
L2 cache
per CPU
Chip Speed
MHz
Model
Table C.8.2.1. iSeries for Domino 8xx Servers
*Note: 1. 5250 OLTP CPW - With a rating of 0, adequate interactive processing is available for a
single 5250 job to perform system administration functions.
2. IBM does not intend to publish CIW ratings for iSeries after V5R2. It is recommended that
the eServer Workload Estimator be used for sizing guidance, available at:
single 5250 job to perform system administration functions.
2. IBM does not intend to publish CIW ratings for iSeries after V5R2. It is recommended that
the eServer Workload Estimator be used for sizing guidance, available at:
na - indicates the rating is not available for the 4-way processor configuration
C.9 V5R2 Additions
In V5R2 the following new iSeries models were introduced:
y
y
890 Base and Standard models
y
840 Base models
y
830 Base and Standard models
Base models represent server systems with “0” interactive capability. Standard Models represent systems
that have interactive features available and also may have Capacity Upgrade on Demand Capability.
that have interactive features available and also may have Capacity Upgrade on Demand Capability.
See Chapter 2, iSeries RISC Server Model Performance Behavior, for a description of the performance
highlights of the new Dedicated servers for Domino models.
highlights of the new Dedicated servers for Domino models.
C.9.1 Base Models 8xx Servers
20910
3220
0
7350
8
4 MB
540
830-0153 (none)
40500
5700
0
12000
12
16 MB
600
840-0158 (none)
77800
10950
0
20200
24
16 MB
600
840-0159 (none)
84100
12900
0
29300
24
1.41 MB*
1300
890-0197 (none)
108900
16700
0
37400
32
1.41 MB*
1300
890-0198 (none)
MCU
Processor
CIW
Interactive
CPW
Processor
CPW
CPUs
L2 cache
per CPU
Chip Speed
MHz
Model
Table C.9.1.1 Base Models 8xx Servers
* 890 Models share L2 cache between 2 processors
C.9.2 Standard Models 8xx Servers
Standard models have an initial offering of processor and interactive capacity with featured upgrades for
activation of additional processors and increased interactive capacity. Processor features are offered
through Capacity Upgrade on Demand, described in C.10 V5R1 Additions.
Standard models have an initial offering of processor and interactive capacity with featured upgrades for
activation of additional processors and increased interactive capacity. Processor features are offered
through Capacity Upgrade on Demand, described in C.10 V5R1 Additions.
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
©
Copyright IBM Corp. 2008
Appendix C CPW, CIW and MCU for System i Platform
353