Siemens ERTEC200 ユーザーズマニュアル
2
ARM946E-S Processor
The ARM946E-S processor is implemented in the ERTEC 200.
This description is based on /1/ and /2/.
This description is based on /1/ and /2/.
2.1 Structure of ARM946E-S
An ARM946E-S processor system is used. The figure below shows the structure of the processor. In addition to the
processor core, the system contains one data cache, one instruction cache, a memory protection unit (MPU), a system
control coprocessor, and a tightly coupled memory. The processor system has an interface to the integrated AHB bus.
processor core, the system contains one data cache, one instruction cache, a memory protection unit (MPU), a system
control coprocessor, and a tightly coupled memory. The processor system has an interface to the integrated AHB bus.
Figure 3: Structure of ARM946E-S Processor System
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ERTEC 200 Manual
Technical data subject to change Version 1.1.0