Intel 5800/120Ld ユーザーズマニュアル
1-8 System Overview
Pentium III Processor
Depending on system configuration, each system includes one or two Pentium III
processors. Each Pentium III processor is packaged in a Single Edge Contact Cartridge
Version 2 (SECC2). The cartridge includes the processor core with an integrated 16 KB
primary (L1) cache, a secondary (L2) cache, and a back cover. The processor
implements the MMX
processors. Each Pentium III processor is packaged in a Single Edge Contact Cartridge
Version 2 (SECC2). The cartridge includes the processor core with an integrated 16 KB
primary (L1) cache, a secondary (L2) cache, and a back cover. The processor
implements the MMX
™
technology and the processor’s numeric coprocessor
significantly increases the speed of floating-point operations.
The processor external interface operates at a maximum of 133 MHz. The second-level
cache is located on the substrate of the processor cartridge. The cache includes burst
pipelined synchronous static RAM (BSRAM).
cache is located on the substrate of the processor cartridge. The cache includes burst
pipelined synchronous static RAM (BSRAM).
System Memory
The system board contains four 168-pin DIMM sockets. Memory is partitioned as four
banks of SDRAM registered DIMMs (PC133 compatible), each providing 72 bits of
noninterleaved memory (64-bit main memory plus ECC). Your system may include
from 64 MB to 4 GB of memory, using up to four DIMMs.
banks of SDRAM registered DIMMs (PC133 compatible), each providing 72 bits of
noninterleaved memory (64-bit main memory plus ECC). Your system may include
from 64 MB to 4 GB of memory, using up to four DIMMs.
System memory begins at address 0 and is continuous (flat addressing) up to the
maximum amount of DRAM installed (exception: system memory is noncontiguous in
the ranges defined as memory holes using configuration registers). The system
supports both base (conventional) and extended memory.
maximum amount of DRAM installed (exception: system memory is noncontiguous in
the ranges defined as memory holes using configuration registers). The system
supports both base (conventional) and extended memory.