HP (Hewlett-Packard) A9834-9001B ユーザーズマニュアル
Chapter 1
Overview
Backplane (Fabric)
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an additional crossbar in a second backplane for a dual backplane configuration. The connection is through a
high-speed cable interface to the second backplane. This 12-cable high-speed interface replaces the flex cable
interface previously used on the Superdome system.
high-speed cable interface to the second backplane. This 12-cable high-speed interface replaces the flex cable
interface previously used on the Superdome system.
Backplane Monitor and Control
The backplane implements the following monitor and control functions.
- Backplane detect and enable functions to and from the CLU
- Backplane LED controls from the CLU
- Backplane JTAG distribution and chains
- Cabinet ID from the CLU
- Reset and power manager FPGA (RPM) and JTAG interface and header for external programming
- XBC reset, configuration and control
- IIC bus distribution to and from the CLU
- Clock subsystem monitor and control
- Power supply monitor and control
- Cell detect, power monitor, reset and rnable to and from the CLU
- JTAG and USB data distribution to and from each cell codule
- Cell ID to each cell module
- OSP FPGA functionality
I2C Bus Distribution
The sx2000 system I2C bus extends to the Superdome backplane (SDBP) assembly through a cable connected
from the CLU subsystem. This cable connects from J17 on the CLU to J64 on the SDBP. The clock and data
signals on this cable are buffered through I2C bus extenders on the CLU and on the backplane.
from the CLU subsystem. This cable connects from J17 on the CLU to J64 on the SDBP. The clock and data
signals on this cable are buffered through I2C bus extenders on the CLU and on the backplane.
The I2C bus is routed to an I2C multiplexer on the backplane where the bus is isolated into four bus
segments. Three bus segments are dedicated to connections to the three RPMs. The remaining segment is
used to daisy-chain the remaining addressable devices on the bus. Each bus segment is addressed through a
port on the I2C multiplexer.
segments. Three bus segments are dedicated to connections to the three RPMs. The remaining segment is
used to daisy-chain the remaining addressable devices on the bus. Each bus segment is addressed through a
port on the I2C multiplexer.
Clock Subsystem
The backplane houses two hot-swap oscillator (HSO) modules. Each HSO board generates a system clock
which feeds into the backplane. Each HSO output is routed to the redundant clock source (RCS) module. The
RCS module accepts input from the two HSO modules and produces a single system clock, which is
distributed on the backplane to all cell modules and XBC ASICs.
which feeds into the backplane. Each HSO output is routed to the redundant clock source (RCS) module. The
RCS module accepts input from the two HSO modules and produces a single system clock, which is
distributed on the backplane to all cell modules and XBC ASICs.