HP (Hewlett-Packard) A9834-9001B ユーザーズマニュアル
Chapter 1
Overview
I/O Subsystem
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I/O Subsystem
The sx2000 I/O backplane (SIOBP) is an update of the sx1000 I/O backplane, with a new set of chips that
increase the board’s internal bandwidth and support the newer PCI-X 2.0 protocol. The sx2000 I/O backplane
uses most of the same mechanical parts as the sx1000 I/O backplane. The connections between the I/O chassis
and the rest of the system have changed. The cell board to I/O backplane links are now multichannel,
high-speed serial (HSS) based rather than the earlier parallel-type interface. Because of this, the sx2000 I/O
backplane is intended to be paired with the sx2000 cell board and is not backward compatible with earlier
Superdome cell boards. The term “PCI-X I/O chassis” refers to the assembly containing an SIOBP. All slots
are capable of supporting both PCI and PCI-X cards.
increase the board’s internal bandwidth and support the newer PCI-X 2.0 protocol. The sx2000 I/O backplane
uses most of the same mechanical parts as the sx1000 I/O backplane. The connections between the I/O chassis
and the rest of the system have changed. The cell board to I/O backplane links are now multichannel,
high-speed serial (HSS) based rather than the earlier parallel-type interface. Because of this, the sx2000 I/O
backplane is intended to be paired with the sx2000 cell board and is not backward compatible with earlier
Superdome cell boards. The term “PCI-X I/O chassis” refers to the assembly containing an SIOBP. All slots
are capable of supporting both PCI and PCI-X cards.
A new concept for the sx2000 is that of a fat rope. A fat rope is logically one rope that has 32 wires. It consists
of two single ropes but has the four command wires in the second single rope removed. The concept of a single
rope remains unchanged. It has 18 signals, of which 10 are bidirectional, single-ended address and data bits.
There are also two pairs of unidirectional, single-ended lines that carry commands in each direction and a
differential strobe pair for each direction. These are all “enhanced ropes,” which support double the
bandwidth of plain ropes and additional protocol behavior. Ropes transfer source-synchronous data on both
edges of the clock and can run at either of two speeds.
of two single ropes but has the four command wires in the second single rope removed. The concept of a single
rope remains unchanged. It has 18 signals, of which 10 are bidirectional, single-ended address and data bits.
There are also two pairs of unidirectional, single-ended lines that carry commands in each direction and a
differential strobe pair for each direction. These are all “enhanced ropes,” which support double the
bandwidth of plain ropes and additional protocol behavior. Ropes transfer source-synchronous data on both
edges of the clock and can run at either of two speeds.
The major components in the I/O chassis are the system bus adapter (SBA) ASIC and 12 logical bus adapter
(LBA) ASICs. The high speed serial (HSS) links (one inbound and one outbound) are a group of 20 high-speed
serial differential connections using a cable that allows the I/O chassis to be located as much as 14 feet away
from the cell board. This allows the use of an I/O expansion cabinet to provide more I/O slots than will fit in
the main system cabinet.
(LBA) ASICs. The high speed serial (HSS) links (one inbound and one outbound) are a group of 20 high-speed
serial differential connections using a cable that allows the I/O chassis to be located as much as 14 feet away
from the cell board. This allows the use of an I/O expansion cabinet to provide more I/O slots than will fit in
the main system cabinet.
Enhanced ropes are fast, narrow links that are connected singly or in pairs between the SBA and four specific
LBAs. Fat ropes are enhanced dual-width ropes that are treated logically as a single rope.
LBAs. Fat ropes are enhanced dual-width ropes that are treated logically as a single rope.
A PCI-X I/O chassis is an assembly consisting of four printed circuit assemblies (the PCI-X I/O backplane, the
PCI-X I/O power board, the PCI-X I/O power transfer board, and the doorbell board) plus the necessary
mechanical components required to support 12 PCI card slots.
PCI-X I/O power board, the PCI-X I/O power transfer board, and the doorbell board) plus the necessary
mechanical components required to support 12 PCI card slots.
The master I/O backplane provides easy connectivity for the I/O chassis. The HSS link and utilities signals
come through the master I/O backplane. Most of the utilities signals travel between the UGUY and the I/O
backplane, with a few passing through to the I/O power board. The I/O power board contains all the power
converters that produce the various voltages needed on the I/O backplane. Both the I/O backplane and the I/O
power board have FRU EEPROMs. An I/O power transfer board is a simple assembly that provides the
electrical connections for power and utility signals between the I/O backplane and I/O power board.
come through the master I/O backplane. Most of the utilities signals travel between the UGUY and the I/O
backplane, with a few passing through to the I/O power board. The I/O power board contains all the power
converters that produce the various voltages needed on the I/O backplane. Both the I/O backplane and the I/O
power board have FRU EEPROMs. An I/O power transfer board is a simple assembly that provides the
electrical connections for power and utility signals between the I/O backplane and I/O power board.
PCI-X Backplane Functionality
The majority of the functionality of a PCI-X I/O backplane is provided by a single SBA ASIC plus 12 LBA
ASICs (one per PCI slot). A dual-slot-hot plug controller chip plus related logic is also associated with each
pair of PCI slots. The SBA is the primary I/O component. Upstream, the SBA communicates directly with the
cell controller CC ASIC of the host cell board via a high-bandwidth logical connection known as the HSS link.
Downstream, the SBA spawns 16 logical ropes that communicate with the LBA PCI interface chips. Each PCI
chip produces a single 64-bit PCI-X bus supporting a single PCI or PCI-X add-in card. The SBA and the CC
are components of the sx2000 and are not compatible with the legacy or Integrity CECs.
ASICs (one per PCI slot). A dual-slot-hot plug controller chip plus related logic is also associated with each
pair of PCI slots. The SBA is the primary I/O component. Upstream, the SBA communicates directly with the
cell controller CC ASIC of the host cell board via a high-bandwidth logical connection known as the HSS link.
Downstream, the SBA spawns 16 logical ropes that communicate with the LBA PCI interface chips. Each PCI
chip produces a single 64-bit PCI-X bus supporting a single PCI or PCI-X add-in card. The SBA and the CC
are components of the sx2000 and are not compatible with the legacy or Integrity CECs.